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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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DLPA2000 Datenblatt(PDF) 4 Page - Texas Instruments |
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DLPA2000 Datenblatt(HTML) 4 Page - Texas Instruments |
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4 / 63 page  Table 5-1. Test Pins and General Control PIN I/O TYPE(4) DESCRIPTION NAME NO. HWTEST_EN C10 I 6 Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation. PARKZ C13 I 6 DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD may not be achieved with the fast park operation; therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPAxxxx interrupt output signal. JTAGTCK P12 I 6 TI internal use. Leave this pin unconnected. JTAGTDI P13 I 6 TI internal use. Leave this pin unconnected. JTAGTDO1 N13(1) O 1 TI internal use. Leave this pin unconnected. JTAGTDO2 N12(1) O 1 TI internal use. Leave this pin unconnected. JTAGTMS1 M13 I 6 TI internal use. Leave this pin unconnected. JTAGTMS2 N11 I 6 TI internal use. Leave this pin unconnected. JTAGTRSTZ P11 I 6 TI internal use. This pin must be tied to ground, through an external resistor for normal operation. Failure to tie this pin low during normal operation can cause start up and initialization problems.(2) RESETZ C11 I 6 Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is de-asserted. No signals are in their active state while RESETZ is asserted. This pin is typically connected to the RESETZ pin of the DLPA200x. TSTPT_0 R12 I/O 1 Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as outputs.(2) (3) Normal use: reserved for test output. Leave open for normal use. Note: An external pullup may put the DLPC34xx in a test mode. See Section 7.3.6 for more information. TSTPT_1 R13 I/O 1 TSTPT_2 R14 I/O 1 TSTPT_3 R15 I/O 1 TSTPT_4 P14 I/O 1 TSTPT_5 P15 I/O 1 TSTPT_6 N14 I/O 1 TSTPT_7 N15 I/O 1 (1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is recommended to ensure a logic low. (2) External resistor must have a value of 8 kΩ or less to compensate for pins that provide internal pullup or pulldown resistors. (3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low. (4) See Table 5-11 for type definitions. Table 5-2. Parallel Port Input PIN(1) (2) I/O TYPE(4) DESCRIPTION NAME NO. PARALLEL RGB MODE BT656 INTERFACE MODE PCLK P3 I 11 Pixel clock Pixel clock PDM_CVS_TE N4 I/O 5 Parallel data mask. Programable polarity with default of active high. Optional signal. Unused VSYNC_WE P1 I 11 Vsync(3) Unused HSYNC_CS N5 I 11 Hsync(3) Unused DATAEN_CMD P2 I 11 Data valid Unused DLPC3420 DLPS232 – OCTOBER 2021 www.ti.com 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DLPC3420 |
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