RZSLASHT1 datasheet(3/139 Pages) RENESAS

3 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 3 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

Low power

Low-power consumption

function

 Standby mode (Cortex-R4)

 Sleep mode (Cortex-M3) (for products incorporating an R-IN engine)

 Module stop function

Interrupt

Cortex-R4

vector interrupt

controller (VIC)

 Peripheral function interrupts: 290 sources / 292 sources (for products incorporating an

R-IN engine)

 External interrupts: 20 sources

(NMI, IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)

 Software interrupts: 1 source

 Non-maskable interrupts: 2 sources

 Sixteen levels specifiable for the order of priority

Cortex-M3 nested-type

vector interrupt

controller (NVIC)

(only included in

products incorporating

an R-IN engine)

 Peripheral function interrupts: 101 sources

 External interrupts: 19 sources

(IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)

 Software interrupts: 1 source

 Non-maskable interrupts: 1 source

 Sixteen levels specifiable for the order of priority

External bus

extension

Bus state controller

(BSC)

 The external address space is divided into six areas (CS0 to CS5) for management.

 The following features settable for each area independently.

Bus size (8, 16, or 32 bits): Available sizes depend on the area.

Number of access wait cycles (different wait cycles can be specified for read and write

access cycles in some areas)

Idle wait cycle insertion (between same area access cycles or different area access

cycles)

Specifying the memory to be connected to each area enables direct connection to

SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or

asynchronous). The address/data multiplexed I/O (MPX) interface is also available.

 Outputs a chip select signal (CS0# to CS5#) according to the target area (CS assert or

negate timing can be selected by software)

 SDRAM refresh

Auto refresh or self-refresh mode selectable

 SDRAM burst access

Data transfer

Direct memory access

controller (DMAC)

 2 units (16 channels for unit 0, 16 channels for unit 1)

 Transfer modes: Single transfer mode and block transfer mode

 Transfer size

Unit 0: 1/2/4/16/32/64 bytes

Unit 1: 1/2/4/16 bytes

 Activation sources: External requests (DREQ0 to DREQ2), external interrupts, on-chip

peripheral module requests, and software requests

I/O ports

General-purpose

I/O ports

 320-pin FBGA

I/O pins: 209

Input pins: 9

Pull-up/pull-down resistors: 209

5-V tolerance: 9

 176-pin HLFQFP

I/O pins: 97

Input pins: 5

Pull-up/pull-down resistors: 97

5-V tolerance: 5

Event link controller (ELC)

 Up to 103 event signals can be interlinked with the operation of modules.

 In particular, the operation of timer modules can be started by input event signals.

 Event-linked operation of signals of ports B and E is to be possible.

Multi-function pin controller (MPC)

The locations of input/output functions are selectable from among multiple pins.

Table 1.1

Outline of Specifications (2 / 7)

Classification

Module/Function

Description

RZ/T1 Datenblatt(PDF) 3 Page - Renesas Technology Corp

RZ/T1 Datenblatt(HTML) 3 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL