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RZ/T1 Datenblatt(PDF) 84 Page - Renesas Technology Corp |
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RZ/T1 Datenblatt(HTML) 84 Page - Renesas Technology Corp |
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84 / 139 page ![]() R01DS0228EJ0200 Rev.2.00 Page 84 of 139 Jun. 30, 2025 RZ/T1 Group 2. Electrical Characteristics Note 1. Address pin to be connected to A10 of SDRAM Note 2. DACKn and TENDn are waveforms when “active low” is specified. Figure 2.27 Synchronous DRAM Burst-Write Bus Cycle (Write for 4 Cycles) (with Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) tAD1 tAD1 tCSD1 tRWD1 tBSD tDACD CKIO A25 to A0 CS3#, CS2# RD/WR# RAS# D31 to D0 CAS# DQMUU, DQMUL, DQMLU, DQMLL DACK2 to DACK0 TEND2 to TEND0*2 BS# Tr Tc3 tBSD A12/A11*1 CKE# tAD1 tAD1 tAD1 tAD1 tCSD1 tRWD1 tRASD1 tRASD1 tCASD1 tCASD1 tDACD (High) tWDD2 tWDH2 tDQMD1 tDQMD1 Row address Column address WRITA command Trwl tRWD1 Tc1 Tc2 Tc4 tAD1 tAD1 tAD1 tAD1 WRIT command tWDD2 tWDH2 Trw |
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