RZSLASHT1 datasheet(16/139 Pages) RENESAS

16 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 16 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

Bus state controller (BSC) A25 to A0

Output

Output the address.

D31 to D0

I/O

Input and output the data.

CS0# to CS5#

Output

Output the chip select signal for the external memory or device.

RD#

Output

Outputs the strobe signal which indicates reading is in progress.

RD/WR#

Output

Outputs the strobe signal which indicates the read or write access.

BS#

Output

Outputs the status signal which indicates the start of bus cycles.

AH#

Output

Outputs the address hold signal for the device that uses the

multiplexed I/O bus.

WAIT#

Input

Inputs the external wait control signal which inserts a wait cycle

into the bus cycles.

WE0#

Output

Outputs the write strobe signal to D7 to D0.

WE1#

Output

Outputs the write strobe signal to D15 to D8.

WE2#

Output

Outputs the write strobe signal to D23 to D16.

WE3#

Output

Outputs the write strobe signal to D31 to D24.

DQMLL

Output

Outputs the data mask enable signal to D7 to D0 when SDRAM is

connected.

DQMLU

Output

Outputs the data mask enable signal to D15 to D8 when SDRAM

is connected.

DQMUL

Output

Outputs the data mask enable signal to D23 to D16 when SDRAM

is connected.

DQMUU

Output

Outputs the data mask enable signal to D31 to D24 when SDRAM

is connected.

RAS#

Output

Outputs the low-address strobe signal to the SDRAM. This pin

should be connected to the RAS# pin on the SDRAM.

CAS#

Output

Outputs the column-address strobe signal to the SDRAM. This pin

should be connected to the CAS# pin on the SDRAM.

CKE

Output

Outputs the clock enable signal to the SDRAM. This pin should be

connected to the CKE pin on the SDRAM.

Direct memory access

controller (DMAC)

DREQ0 to DREQ2

Input

Input the DMA transfer request signal from the external device.

DACK0 to DACK2

Output

Output the acknowledge signal which indicates acceptance of the

DMA transfer request from the external device.

TEND0 to TEND2

Output

Output the DMA transfer end signal.

Interrupt

NMI

Input

Inputs the non-maskable interrupt request signal.

IRQ0 to IRQ15

Input

Input the external interrupt request signal.

ETH0_INT, ETH1_INT,

ETH2_INT

Input

Input the Ethernet PHY interrupt request signal.

Table 1.4

Pin Functions (2 / 7)

Classifications

Pin Name

I/O

Description

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