RZSLASHT1 datasheet(4/139 Pages) RENESAS

4 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 4 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

Timers

16-bit timer pulse unit

(TPUa)

 (16 bits × 6 channels) × 2 units*1

 Maximum 16 lines of pulse input/output × 2 units

 Select from among seven or eight counter-input clock signals for each channel

(with maximum operating frequency of 75 MHz)

 Input capture/output compare function

 Counter clear operation (synchronous clearing by compare match/input capture)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Output of PWM waveforms in up to 15 phases × 2 units in PWM mode

 Support for buffered operation, phase-counting mode (two phase encoder input) and

cascade-connected operation (32 bits × 4 channels) depending on the channel.

 PPG output trigger can be generated (unit 0 only)

 Capable of generating conversion start triggers for the A/D converters

 Digital noise filtering of signals from the input capture pins

 Event linking by the ELC (unit 0 only)

Multifunction timer pulse

unit (MTU3a)

 9 channels (16 bits × 8 channels, 32 bits × 1 channel)

 Maximum of 28 pulse-input/output and 3 pulse-input possible

 Select from among 10, 11, 12 or 14 counter-input clock signals for each channel

(with maximum operating frequency of 150 MHz)

 Input capture function

 39 output compare/input capture registers

 Counter clear operation (synchronous clearing by compare match/input capture)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Buffered operation

 Support for cascade-connected operation

 Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

 Complementary PWM output mode

Outputs non-overlapping waveforms for controlling 3-phase inverters

Automatic specification of dead times

PWM duty cycle: Selectable as any value from 0% to 100%

Delay can be applied to requests for A/D conversion.

Non-generation of interrupt requests at crest or trough values of counters can be

selected.

Double buffer configuration

 Reset synchronous PWM mode

Three phases of positive and negative PWM waveforms can be output with desired

duty cycles.

 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2

in cascade connection)

 Counter functionality for dead-time compensation

 Generation of triggers for A/D converter conversion

 A/D converter start triggers can be skipped

 Digital noise filter function for signals on the input capture and external counter clock

pins

 PPG output trigger can be generated

 Event linking by the ELC

Table 1.1

Outline of Specifications (3 / 7)

Classification

Module/Function

Description

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