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RZ/T1 Datenblatt(PDF) 6 Page - Renesas Technology Corp

Teilenummer RZ/T1
Bauteilbeschribung  RZ/T1 Group
PDF  139 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/T1 Datenblatt(HTML) 6 Page - Renesas Technology Corp

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R01DS0228EJ0200 Rev.2.00
Page 6 of 139
Jun. 30, 2025
RZ/T1 Group
1. Overview
Communication
function
Ethernet MAC
(ETHERC)
 1 port (Use of two ports is possible with the Ethernet switch function)
 IEEE802.3 is supported
 10BASE and 100BASE are supported
 Full duplex and half duplex are supported
 Automatic pause packet transmission function
 Auto broadcast suspension function by the pause packet reception
 MII/RMII interface is supported
Ethernet switch
 2-port PHY interfaces
 IEEE802.3
 10BASE and 100BASE are supported
 Full and half duplex
 Hardware switching, lookup, and filtering
 QoS with frame prioritization
 Priority control based on VLAN Priority (IEEE802.1q), which enables priority
reassignment
 Classification and priority assignment based on IPv4 DiffServ Code Point Field, IPv6
Class of Service
 Queue with four priority levels
 Multicasting and broadcasting
 VLAN frame
 IEEE1588 timer module
 Cut-through and hub features
 Device level ring (DLR)
EtherCAT Slave
Controller (ECATC)*2
 1 channel (2 ports)*3
 EtherCAT Slave Controller IP core (made by Beckhoff Automation GmbH) implemented
USB 2.0 HS host/
function module
 1 port
 Compliance with the USB 2.0 specification
 Transfer rate
High speed (480 Mbps), full speed (12 Mbps)
 Communications buffer
Incorporates 1 Kbyte of RAM for host mode
Incorporates 8 Kbytes of RAM for function mode
Serial communication
interface with FIFO
(SCIFA)
 5 channels
 Serial communications modes: Asynchronous, clock synchronous
 On-chip baud rate generator allows selection of the desired bit rate
 Choice of LSB-first or MSB-first transfer
 Both the transmission and reception sections are equipped with 16-byte FIFO buffers,
allowing continuous transmission and reception.
 Bit rate modulation
I2C bus interface (RIICa)
 2 channels
 Supports I2C bus format
 Supports the multi-master
 Max. transfer rate: 400 kbps
 Event linking by the ELC
CAN module (RSCAN)
 2 channels
 Compliance with the ISO11898-1 specification (standard frame and extended frame)
 Message buffers
Max. 64 × 2 channels of reception message buffers, which are used by all channels
16 transmission message buffers per channel
 Max. transfer rate: 1 Mbps
Table 1.1
Outline of Specifications (5 / 7)
Classification
Module/Function
Description



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