RZSLASHT1 datasheet(5/139 Pages) RENESAS

5 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 5 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

Timers

General PWM timer

(GPTa)

 16 bits × 4 channels

 Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for

all channels

 Select from among four counter-input clock signals for each channel

(with maximum operating frequency of 150 MHz)

 2 input/output pins per channel

 2 output compare/input capture registers per channel

 For the 2 output compare/input capture registers of each channel, 4 registers are

provided as buffer registers and are capable of operating as compare registers when

buffering is not in use.

 In output compare operation, buffer switching can be at crests or troughs, enabling the

generation of laterally asymmetrically PWM waveforms.

 Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

 Synchronizable operation of the several counters

 Modes of synchronized operation (synchronized, or displaced by desired times for

phase shifting)

 Generation of dead times in PWM operation

 Through combination of three counters, generation of automatic three-phase PWM

waveforms incorporating dead times

 Starting, clearing, and stopping counters in response to external or internal triggers

 Internal trigger sources: software, and compare-match

 Generation of triggers for A/D converter conversion

 Digital noise filter function for signals on the input capture and external trigger pins

 Event linking by the ELC

Programmable pulse

generator (PPG)

 (4 bits × 4 groups) × 2 units*1

 Pulse output with the MTU3a or TPUa output as a trigger

 Maximum of 32 pulse-output possible

Compare match timer

(CMT)

 (16 bits × 2 channels) × 3 units

 Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 75 MHz)

 Event linking by the ELC (channel 1 of unit 0 only)

Compare match timer W

(CMTW)

 (32 bits × 1 channel) × 2 units

 Compare-match, input-capture input, and output-comparison output are available.

 Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 75 MHz)

 Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

 Digital noise filter function for signals on the input capture pins

 Event linking by the ELC

Watchdog timer (WDTA)

 14 bits × 1 channel

Products incorporating an R-IN engine: 14 bits × 2 channels

 Select from among six counter-input clock signals for each channel (with maximum

operating frequency of 75 MHz)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: Low-speed on-chip oscillator (LOCO)/2

Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256 (with maximum operating frequency of 120

kHz)

Port output enable 3

(POE3)

 Control of the high-impedance state of the MTU3a / GPTa's waveform output pins

 Initiation by inputs on 4 pins, POE0#, POE4#, POE8#, and POE10#

 Initiation on detection of short-circuited outputs (detection of simultaneous PWM output

to the active level)

 Initiation by input clock oscillation-stoppage detection, PLL oscillation abnormality

detection, or software

 Additional programming of output control target pins is enabled

Table 1.1

Outline of Specifications (4 / 7)

Classification

Module/Function

Description

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