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RZ/T1 Datenblatt(PDF) 68 Page - Renesas Technology Corp

Teilenummer RZ/T1
Bauteilbeschribung  RZ/T1 Group
PDF  139 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
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RZ/T1 Datenblatt(HTML) 68 Page - Renesas Technology Corp

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R01DS0228EJ0200 Rev.2.00
Page 68 of 139
Jun. 30, 2025
RZ/T1 Group
2. Electrical Characteristics
Note 1. Take the number of cycles of waiting that suits the system configuration into consideration with regard to the fmax value for
CKIO (the external bus clock). When CKIO is running at 50 MHz or a higher frequency, set the B0 bit of the driving ability control
register (DSCR) to 1 to select high-drive output. When CKIO is running at less than 50 MHz, normal output of CKIO can be used
(DSCR.B0 bit = 0).
Note 2. Notation of 1/2tCKcyc in the delay time, setup time, and hold time shows 1/2 cycles from the clock rising edge, that is, the
reference of clock falling.
Note 3. These are values when SDRAM (TYPE[2:0] bits = 100b) is selected in the CSn space bus control register (CSnBCR) and high-
drive output (B0 bit = 1) is selected in the driving ability control register (DSCR) for CKIO.
Note 4. These are values when high-drive output (B0 bit = 1) and normal output (B0 bit = 0) are respectively selected in the driving
ability control register (DSCR) for CKIO.
Write data hold time 2
tWDH2
2
―
ns
Figure 2.24 to
Figure 2.27,
Figure 2.31 to
Figure 2.33
Write data hold time 4
tWDH4
0
―
ns
Figure 2.12 to
Figure 2.16
WAIT# setup time*4
High-drive output
tWTS
1/2tCKcyc + 4.5
―
ns
Figure 2.13 to
Figure 2.19
Normal output
1/2tCKcyc + 8
―
ns
WAIT# hold time
tWTH
1/2tCKcyc + 3.5
―
ns
Figure 2.13 to
Figure 2.19
RAS# delay time 1
tRASD1
2
10
ns
Figure 2.20 to
Figure 2.36
CAS# delay time 1
tCASD1
2
10
ns
Figure 2.20 to
Figure 2.36
DQM delay time 1
tDQMD1
2
10
ns
Figure 2.20 to
Figure 2.33
CKE delay time 1
tCKED1
2
10
ns
Figure 2.35
AH# delay time
tAHD
1/2tCKcyc
1/2tCKcyc + 10
ns
Figure 2.16
Multiplex address delay
time
tMAD
―
10
ns
Figure 2.16
Multiplex address hold
time
tMAH
1
―
ns
Figure 2.16
Address setup time to
AH#
tAVVH
1/2tCKcyc – 2
―
ns
Figure 2.16
DACK/TEND delay time
tDACD
See DMAC timing
See DMAC timing
ns
Figure 2.12 to
Figure 2.33
Table 2.17
Bus Timing (2 / 2)
Output load conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF
Item
Symbol
CKIO = 1/tCKcyc*1
Unit
Reference
Figure
Min.
Max.



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