RZSLASHT1 datasheet(14/139 Pages) RENESAS

14 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 14 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

1.4

Block Diagram

Figure 1.1 shows a block diagram of a 320-pin device.

ETHERC:

Ethernet controller

ECATC:

EtherCAT slave controller

DMAC:

DMA controller

BSC:

Bus state controller

SPIBSC:

SPI multi I/O bus controller

WDTA:

Watchdog timer

IWDTa:

Independent watchdog timer

SCIFA:

Serial communication interface with FIFO

RSPIa:

Serial peripheral interface

USB:

USB 2.0 HS host/function module

VIC:

Vector interrupt controller

NVIC:

Nested-type vector interrupt controller

MPU:

Memory protection unit

ELC:

Event link controller

TPUa:

16-bit timer pulse unit

MTU3a:

Multi-function timer pulse unit 3

POE3:

Port output enable 3

GPTa:

General-purpose PWM timer

PPG:

Programmable pulse generator

CMT:

Compare match timer

CMTW:

Compare match timer W

RIICa:

I2C bus interface

RSCAN:

CAN module

SSI:

Serial sound interface

DSMIF:

ΔΣ interface

CRC:

CRC (cyclic redundancy check) calculator

CLMA:

Clock monitor circuit

DOC:

Data operation circuit

ECM:

Error control module

Note 1. Combining the Ethernet controller and the

EtherCAT slave controller (optional) makes a total

of three ports. The Ethernet controller can support

two ports with the use of the Ethernet switch.

Figure 1.1

Block Diagram

CMT × 2 ch (unit 1)

CMTW × 1 ch (unit 1)

CMTW × 1 ch (unit 0)

CMT × 2 ch (unit 2)

BSC

Cortex-R4

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

12-bit A/D converter × 16 ch (unit 1)

MTU3a × 9 ch

WDTA × 1 ch

Products incorporating an R-IN engine: WDTA × 2ch

RIIC × 2 ch

CRC

IWDTa

USB

× 1 port

RSCAN × 2 ch

POE3

TPUa × 6 ch (unit 0)

CMT × 2 ch (unit 0)

PPG (unit 1)

PPG (unit 0)

RSPIa × 4 ch

Temperature sensor

GPTa × 4 ch

Port D

Port E

Port F

Port G

Port H

Port J

Port K

Port L

MPU

SCIFA × 5 ch

DOC

CLMA

On-chip

extended

SRAM

with ECC

Port P

Port M

Port N

Port T

Port R

Port S

VIC

TCM

Cortex-M3

MPU

Clock

generation

circuit

NVIC

ELC

TPUa × 6 ch (unit 1)

SSI

DSMIF × 1 ch (unit 1)

DSMIF × 3 ch (unit 0)

ECM

12-bit A/D converter × 8 ch (unit 0)

SPIBSC

Port U

ETHERC × 1 port

ECATC × 2 ports

DMAC ×

16 ch

(unit 0)

DMAC ×

16 ch

(unit 1)

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