RZSLASHT1 datasheet(8/139 Pages) RENESAS

8 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 8 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

Note 1. One unit for 176-pin devices (only unit 0 is provided)

Note 2. EtherCAT is a registered trademark of Beckhoff Automation GmbH, Germany. (optional)

Note 3. Not included in 176-pin devices.

Note 4. See Table 1.3, List of Products, for the products that have the secure boot mode. Details of these optional functions will only be

disclosed after completion of a binding non-disclosure agreement. For details, contact our sales representative.

Note 5. This applies to the devices with the encoder interfaces. For details, contact our sales representative.

Note 6. For use of two channels, use them in combination of any two protocols among EnDat2.2, BiSS-C, FA-CODER, and A-format.

Safety

function

Protects important registers from being overwritten in cases where a program runs out of

control.

CRC calculator (CRC)

 CRC code generation for arbitrary amounts of data in 8-, 16-, or 32-bit units

 Select any of four generating polynomials:

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 (32-

Ethernet),

X16 + X12 + X5 + 1 (16-CCITT),

X8 + X4 + X3 + X2 + 1 (8-SAEJ1850),

X8 + X5 + X3 + X2 + X + 1 (8-0x2F)

Input clock oscillation

stop function

Input clock oscillation stop detection: Available

Clock monitor circuit

(CLMA)

Monitors the abnormal output clock frequency from the PLL circuit or low-speed on-chip

oscillator.

Data operation circuit

(DOC)

The function to compare, add, or subtract 16-bit data

Error control module

(ECM)

 Generates an interrupt, internal reset, or error output for the error signal input from each

module.

 Time-out function

 The error control is duplicated in the master and the checker.

Security

Secure boot mode*4

As an option, a boot mode with encryption as a security function is available.

Encoder interfaces*5

 2 channels*6

 EnDat 2.2, BiSS-C, FA-CODER, A-format, and HIPERFACE DSL-compliant interfaces

 Frequency-divided output from an encoder

Power supply voltage

VDD = PLLVDD0 = PLLVDD1 = DVDD_USB = 1.14 to 1.26 V

VCCQ33 = AVCC0 = AVCC1 = VREFH0 = VREFH1 = VDD33_USB = 3.0 to 3.6 V

Operating temperature

Tj = -40 to +125°C

Package

320-pin FBGA: 17 × 17 mm, 0.8-mm pitch PRBG0320GA-A

320-pin FBGA: 17 × 17 mm, 0.8-mm pitch PRBG0320GB-A

320-pin FBGA: 17 × 17 mm, 0.8-mm pitch PLBG0320GB-A

176-pin HLFQFP: 20 × 20 mm, 0.4-mm pitch PLQP0176LD-A

Debugging interface

 CoreSight architecture designed by Arm

 Debugging function by the JTAG/SWD interface, and trace function by the trace port/

SWV interface

Table 1.1

Outline of Specifications (7 / 7)

Classification

Module/Function

Description

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