RZSLASHT1 datasheet(2/139 Pages) RENESAS

2 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 2 of 139

Jun. 30, 2025

RZ/T1 Group

1. Overview

Overview

1.1

Outline of Specifications

This LSI circuit is a high-performance MCU equipped with the Arm® Cortex®-R4 processor with FPU and Cortex-M3

processor (for products incorporating an R-IN engine), and incorporating integrated peripheral functions necessary for

system configuration. Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of

products in different packages.

Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs

depending on the pin number on the package. For details, see Table 1.2, List of Functions.

Table 1.1

Outline of Specifications (1 / 7)

Classification

Module/Function

Description

CPU

Central processing unit

(Cortex-R4)

 Maximum operating frequency

320-pin FBGA: 300 MHz/450 MHz/600 MHz

176-pin HLFQFP: 450 MHz

 32-bit CPU Cortex-R4 designed by Arm (core revision r1p4)

 Address space: 4 Gbytes

 Instruction cache: 8 Kbytes (with ECC)

 Data cache: 8 Kbytes (with ECC)

 Tightly coupled memory (TCM)

ATCM: 512 Kbytes (with ECC)

BTCM: 32 Kbytes (with ECC)

 Instruction set: Arm v7-R architecture, so support includes Thumb® and Thumb-2

 Data arrangement

Instructions: Little endian

Data: Little endian

 Memory protection unit (MPU)

Central processing unit

(Cortex-M3)

(for products

incorporating an R-IN

engine)

 Operating frequency: 150 MHz

 32-bit CPU Cortex-M3 designed by Arm (core revision r2p1)

 Address space: 4 Gbytes

 Instruction set: Arm v7-M architecture, so support includes Thumb® and Thumb-2

 Data arrangement

Instructions: Little endian

Data: Little endian

 Memory protection unit (MPU)

FPU

(Cortex-R4)

 Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and

square-root operations at single- and double-precision.

 Registers

32-bit single-word registers: 32 bits × 32

(can be used as 16 double-word registers: 64 bits × 16)

Memory

On-chip extended

SRAM with ECC

 Capacity: Up to 1 Mbyte

 Operating frequency: 150 MHz

 SEC-DED (single error correction/double error detection)

Operating modes

 The operating mode can be selected from the following three boot modes

SPI boot mode (for booting up from serial flash memory)

16-bit bus boot mode (NOR Flash)

32-bit bus boot mode (NOR Flash)

Clock

Clock generation circuit

 The input clock can be selected from an external clock or external resonator.

 Detection of input clock oscillation stopping

 The following clocks are generated.

CPU clock: 300/450/600 MHz (max.)

System clock: 150 MHz (fixed)

High-speed peripheral module clock: 150 MHz (fixed)

Low-speed peripheral module clock: 75 MHz (fixed)

ADCCLK in the 12-bit A/D converter (S12ADCa): 60 MHz (max.)

External bus clock: 75 MHz (max.)

Low-speed on-chip oscillator: 240 kHz (fixed)

Reset

RES# pin reset, error control module (ECM) reset, software reset

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