RZSLASHT1 datasheet(1/139 Pages) RENESAS

Teilenummer	RZ/T1

Bauteilbeschribung	RZ/T1 Group

PDF	139 Pages

Scroll/Zoom	100%

Hersteller	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

1 / 139 page

RZ/T1 Group

Datasheet

R01DS0228EJ0200 Rev.2.00

Page 1 of 139

Jun. 30, 2025

Features

■ On-chip 32-bit Arm Cortex-R4 processor



High-speed realtime control with maximum operating frequency of

300/450/600 MHz

Capable of 498/747/996 DMIPS (in operation at 300/450/600

MHz)



On-chip 32-bit Arm Cortex-R4 (revision r1p4)



Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes



Instruction cache/data cache with ECC: 8 Kbytes per cache



High-speed interrupt



The FPU supports addition, subtraction, multiplication, division,

multiply-and-accumulate, and square-root operations at single-

precision and double-precision.



Harvard architecture with 8-stage pipeline



Supports the memory protection unit (MPU)



Arm CoreSight architecture, includes support for debugging

through JTAG and SWD interfaces

■ On-chip 32-bit Arm Cortex-M3 processor

(in products incorporating an R-IN engine)



150-MHz operating frequency



On-chip 32-bit Arm Cortex-M3 (revision r2p1)



RISC Harvard architecture with 3-stage pipeline



Supports the memory protection unit (MPU)

■ Low power consumption



Standby mode, sleep mode, and module stop function

■ On-chip extended SRAM



Up to 1 Mbyte of the on-chip extended SRAM with ECC



150 MHz

■ Data transfer



DMAC: 16 channels × 2 units



DMAC for the Ethernet controller: 1 channel

■ Event link controller



Module operations can be started by event signals rather than by

interrupt handlers.



Linked operation of modules is available even while the CPU is in

the sleep state.

■ Reset and power supply voltage control



Four reset sources including a pin reset



Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V

(internal)

■ Clock functions



External clock/oscillator input frequency: 25 MHz



CPU clock frequency: Up to 300/450/600 MHz



Low-speed on-chip oscillator (LOCO): 240 kHz

■ Independent watchdog timer



Operated by a clock signal obtained by frequency-dividing the

clock signal from the low-speed on-chip oscillator: Up to 120 kHz

■ Safety functions



Register write protection, input clock oscillation stop detection,

CRC, IWDTa, and A/D self-diagnosis



An error control module is incorporated to generate a pin signal

output, interrupt, or internal reset in response to errors originating

in the various modules.

■ Security functions (optional)*2



Boot mode with security through encryption

■ Encoder interfaces (optional)



2 channels*3



EnDat 2.2, BiSS-C, FA-CODER, A-format, and HIPERFACE

DSL-compliant interfaces*4



Frequency-divided output from an encoder

■ Various communications interfaces



Ethernet

- EtherCAT slave controller: 2 ports (optional)

- Ethernet MAC: 1 port (an Ethernet switch is not used)

or

- Ethernet MAC: 1 port (an Ethernet switch to support 2 ports is

used)



USB 2.0 high-speed host/function : 1 channel



CAN (compliant with ISO11898-1): 2 channels (max.)



SCIFA with 16-byte transmission and reception FIFOs: 5 channels



I2C bus interface: 2 channels for transfer at up to 400 kbps



RSPIa: 4 channels

 SPIBSC: Provides a single interface for multi-I/O compatible

serial flash memory

■ External address space



Buses for high-speed data transfer at 75 MHz (max.)



Support for up to 6 CS areas



8-, 16-, or 32-bit bus space is selectable per area

■ Up to 33 extended-function timers



16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4

channels): Input capture, output compare, PWM waveform output



16-bit CMT (6 channels), 32-bit CMTW (2 channels)

■ Serial sound interface (1 channel)

■ ΔΣ interface



Up to 4 ΔΣ modulators are connectable externally.

■ 12-bit A/D converters



12 bits × 2 units (max.)

(8 channels for unit 0; 16 channels for unit 1)



Self diagnosis



Detection of analog input disconnection

■ Temperature sensor for measuring temperature

within the chip

■ General-purpose I/O ports



5-V tolerance, open drain, input pull-up

■ Multi-function pin controller



The locations of input/output functions for peripheral modules are

selectable from among multiple pins.

■ Operating temperature range



Tj = -40°C to +125°C

Tj: Junction temperature

PRBG0320GA-A 17 × 17 mm, 0.8-mm pitch

PRBG0320GB-A 17 × 17 mm, 0.8-mm pitch

PLBG0320GB-A 17 × 17 mm, 0.8-mm pitch

PLQP0176LD-A 20 × 20 mm, 0.4-mm pitch

R01DS0228EJ0200

Rev.2.00

Jun. 30, 2025

300 MHz/450 MHz/600 MHz, MCU with Arm® Cortex®-R4 and -M3*1, on-chip FPU, 498/747/996

DMIPS, up to 1 Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.0 high-speed,

CAN, various communications interfaces such as an SPI multi-I/O bus controller, ΔΣ interface, safety

functions, encoder interfaces*1, and security functions*1

Note 1.

Optional

Note 2.

Details of these optional functions will only be disclosed after completion of a binding non-disclosure agreement. For details, contact our sales

representative.

Note 3.

For use of two channels, use them in combination of any two protocols among EnDat2.2, BiSS-C, FA-CODER, and A-format.

Note 4.

BiSS is a registered trademark of iC-Haus GmbH.

RZ/T1 Datenblatt(PDF) 1 Page - Renesas Technology Corp

RZ/T1 Datenblatt(HTML) 1 Page - Renesas Technology Corp

Ähnliche Teilenummer - RZ/T1

Ähnliche Beschreibung - RZ/T1

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL