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RZ/T1 Datenblatt(PDF) 7 Page - Renesas Technology Corp |
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RZ/T1 Datenblatt(HTML) 7 Page - Renesas Technology Corp |
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7 / 139 page ![]() R01DS0228EJ0200 Rev.2.00 Page 7 of 139 Jun. 30, 2025 RZ/T1 Group 1. Overview Communication function Serial peripheral interface (RSPIa) 4 channels RSPI transfer facility Using the MOSI (master out slave in), MISO (master in slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Buffered structure Double buffers for both transmission and reception RSPCK can be stopped automatically with the reception buffer full for master reception Event linking by the ELC SPI multi I/O bus controller (SPIBSC) 1 channel One serial flash memory with multiple I/O bus sizes (single/dual/quad) can be connected. External address space read mode (built-in read cache) SPI operating mode Clock polarity and clock phase can be selected. Maximum transfer rate: 300 Mbps (for quad) Serial sound interface (SSI) 1 channel Duplex communication Support of various serial audio formats Support of master and slave functions Generation of serial bit clock Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats Support of eight-stage FIFO for transmission and reception Support of WS continue mode in which the SSIWS signal is not stopped. ΔΣ interface (DSMIF) 4 channels (unit 0: 3 channels, unit 1: 1 channel) Up to 4 ΔΣ modulators are externally connectable Sync filter can be selected as first, second, or third order 12-bit A/D converter (S12ADCa) 12 bits × 2 units (unit 0: 8 channels, unit 1: 16 channels)*1 12-bit resolution Conversion time Unit 0: 0.483 µs per channel Unit 1: 0.883 µs per channel Operating mode Scan mode (single scan mode, continuous scan mode, or group scan mode) Group A priority control (only for group scan mode) Sample-and-hold function Common sample-and-hold circuit included In addition, channel-dedicated sample-and-hold function (4 channels: in unit 0 only) included Sampling variable Sampling time can be set up for each channel Self-diagnostic function The self-diagnostic function internally generates three analog input voltages (unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: VREFL1, VREFH1 × 1/2, VREFH1) Double trigger mode (A/D conversion data duplicated) Detection of analog input disconnection Three ways to start A/D conversion Software trigger, timer (MTU3a, GPTa, TPUa) trigger, external trigger Event linking by the ELC Temperature sensor 1 channel Relative precision: ±1°C The voltage of the temperature is converted into a digital value by the 12-bit A/D converter (unit 0). Table 1.1 Outline of Specifications (6 / 7) Classification Module/Function Description |
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