SPRUG18 datasheet(112/214 Pages) TI

112 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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7.7

Reset Controller

The reset controller detects the different type of resets supported on the device and manages the

distribution of those resets throughout the device.

The C6474 device has several types of resets: power-on reset, warm reset, system reset, and CPU reset.

Table 7-18 explains further the types of reset, the reset initiator, and the effects of each reset on the chip.

Table 7-18. Reset Types

TYPE

INITIATOR

EFFECT(S)

Power-on Reset

POR pin

Resets the entire chip including the test and emulation logic.

Warm Reset

XWRST pin

Resets everything except for the test and emulation logic PLL2, AIF, and FSYNC. Emulation

stays alive during warm reset.

System Reset

Emulator

A system reset maintains memory contents and does not reset the test and emulation

Serial RapidIO

circuitry. The device configuration pins are also not re-latched and the state of the

peripherals (enabled/disabled) are also not affected.

CPU Local Reset

Watchdog Timer

CPU local reset.

7.7.1

Power-on Reset (POR Pin)

Power-on Reset is a special reset needed when powering on the DSP. The device is globally reset

through the assertion of the active-low Power-on Reset (POR) input. The power-on reset is intended to be

asserted to the device while the system power supplies are ramped.

For power-on reset, the main PLL Controller comes up in bypass and the PLL is not enabled. Other resets

do not affect the state of the PLL or the dividers in the PLL Controller. For the secondary PLL Controller,

this is different as the PLL is enabled and clocking always when POR is not asserted.

The following sequence must be followed during a power-on reset.

1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After

the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set

to their reset state and will remain at their reset state until otherwise configured by their respective

peripheral. All peripherals that are power managed, are disabled after a Power-on Reset and must be

enabled through the Device State Control registers (for more details, see Section 3.2, Peripheral

Selection After Device Reset.

2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset

synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in

reset.

3. POR must be held active until all supplies on the board are stable then for at least an additional 100

μs.

4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. PLL2 is

taken out of reset and begins its locking sequence, and all power-on device initialization also begins.

5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time,

PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of

both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their

respective system reference clocks. After the pause, the system clocks are restarted at their default

divide by settings.

6. The device is now out of reset and device execution begins as dictated by the selected boot mode.

112

Peripheral Information and Electrical Specifications

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