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SPRUG18 Datenblatt(PDF) 114 Page - Texas Instruments |
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SPRUG18 Datenblatt(HTML) 114 Page - Texas Instruments |
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114 / 214 page ![]() TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com 7.7.6 Reset Controller Register The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see Table 7-19). 7.7.6.1 Reset Type Status Register Description The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The reset type status register is shown in Figure 7-6 and described in Table 7-19. 31 16 Reserved R-0 15 4 3 2 1 0 Reserved SRST Rsvd WRST POR R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-6. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4] Table 7-19. Reset Type Status Register (RSTYPE) Field Descriptions BIT FIELD VALUE DESCRIPTION 31:4 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has not effect. 3 SRST System Reset. 0 System Reset was not the last reset to occur. 1 System Reset was the last reset to occur. 1 WRST Warm Reset. 0 Warm Reset was not the last reset to occur. 1 Warm Reset was the last reset to occur. 2 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has not effect. 0 POR Power-on Reset. 0 Power-on Reset was not the last reset to occur. 1 Power-on Reset was the last reset to occur. 114 Peripheral Information and Electrical Specifications Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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