SPRUG18 datasheet(113/214 Pages) TI

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TMS320C6474

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SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.7.2

Warm Reset

A warm reset will reset everything on the chip except the AIF, FSYNC, PLLs, PLL Controllers, test, and

emulation logic. POR should also remain de-asserted during this time.

1. XWRST pin is pulled active low for a minimum of 24 CLKIN1 cycles. The reset signals flow to the

modules reset by warm reset and sends a tri-state signal to most the I/O pads, to prevent off chip

contention.

2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

3. XWRST pin can now be released. A minimal device initialization begins to occur. Note that

configuration pins are not re-latched and clocking is unaffected within the device.

4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

During warm reset, the DDR2 SDRAM memory content can be retained if the user places the DDR2

SDRAM in self-refresh mode before invoking the warm reset; however, warm reset will reset the DDR2

EMIF registers. The software needs to re-program all DDR2 EMIF registers to correct values after warm

reset.

7.7.3

System Reset

System reset is initiated by the emulator or by the RapidIO module. It is triggered by clicking on the

Debug

→ Advanced Resets → System Reset menu in Code Composer Studio using the emulator.

System reset is also triggered by RIOINT[6], which is connected to the reset controller. It is considered a

soft reset, meaning memory contents are maintained, it does not affect the clock logic, or the power

control logic of the peripherals.

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to

propagate through the system. Internal system clocks are not affected. PLLs also remain locked.

2. The boot sequence is started after the system clocks are restarted. Since the configuration pins

(including the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as

shown in the DEVSTAT register, are used to select the boot mode.

7.7.4

CPU Reset

(Timer 64 3, 4, and 5) can provide a local CPU reset if they are setup in watchdog mode. Timer64 3, 4,

and 5 are allowed to reset C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+

Megamodule Core 2, respectively.

7.7.5

Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority

reset request. The reset request priorities are as follows (high to low):

•

Power-on Reset

•

Warm Reset

•

System Reset

•

CPU Reset

Peripheral Information and Electrical Specifications

113

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