AM79C940VCW datasheet(23/122 Pages) AMD

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AMD

Am79C940

STDCLK Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

STDCLK Output

10BASE-T

STDCLK Output

DAI Port

STDCLK Output

GPSI

STDCLK Input

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

CLSN

Collision

(Input/Output)

An external indication that a collision condition has been

detected by the (internal or external) Medium Attach-

ment Unit (MAU), and that signals from two or more

nodes are present on the network. When the AUI port is

selected (PORTSEL [1–0] = 00), CLSN will be activated

when the CI

± input pair is receiving a collision indication

from the external transceiver. CLSN will be asserted

high for the entire duration of the collision detection, but

will not be asserted during the SQE Test message fol-

lowing a transmit message on the AUI. When the

10BASE-T port is selected (PORTSEL [1–0] = 01),

CLSN will be asserted high when simultaneous transmit

and receive activity is detected (logically detected when

TXD

±/TXP± and RXD± are both active). When the DAI

port is selected (PORTSEL [1–0] = 10), CLSN will be as-

serted high when simultaneous transmit and receive ac-

tivity is detected (logically detected when RXCRS and

TXEN are both active). When the GPSI port is selected

(PORTSEL [1–0] = 11), an input from the external

Manchester encoder/decoder signaling the MACE de-

vice that a collision condition has been detected on the

network, and any receive frame in progress should be

aborted.

External Address Detection Interface

(EADI )

SF/BD

Start Frame/Byte Delimiter

(Output)

The external indication that a start of frame delimiter has

been received. The serial bit stream will follow on the

Serial Receive Data pin (SRD), commencing with the

destination address field. SF/BD will go high for 4 bit

times (400 ns) after detecting the second 1 in the SFD of

a received frame. SF/BD will subsequently toggle every

400 ns (1.25 MHz frequency) with the rising edge indi-

cating the start (first bit) in each subsequent byte of the

received serial bit stream. SF/BD will be inactive during

frame transmission.

SRD

Serial Receive Data

(Output)

SRD is the decoded NRZ data from the network. It is

available for external address detection. Note that when

the 10BASE-T port is selected, transition on SRD will

only occur during receive activity. When the AUI or DAI

port is selected, transition on SRD will occur during both

transmit and receive activity.

CLSN Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

CLSN Output

10BASE-T

CLSN Output

DAI Port

CLSN Output

GPSI

CLSN Input

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

AM79C940VCW Datenblatt(PDF) 23 Page - Advanced Micro Devices

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