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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AM79C940VCW Datenblatt(PDF) 78 Page - Advanced Micro Devices |
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AM79C940VCW Datenblatt(HTML) 78 Page - Advanced Micro Devices |
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78 / 122 page  AMD 78 Am79C940 Programmer’s Register Model (continued) Addr Mnemonic Contents R/W 14 PLSCC Physical Layer Signalling (PLS) Configuration Control 08 XMTSEL Transmit Mode Select: 1 →DO± = 1 during IDLE 06 PORTSEL [1:0]—Port Select (2 bits) 00 AUI selected 01 10BASE-T selected 10 DAI port selected 11 GPSI selected 01 ENPLSIO Enable Status 15 PHYCC Physical Layer (PHY) Configuration Control R/W 80 LNKFL Link Fail—Reports 10BASE-T receive inactivity 40 DLNKTST Disable Link Test—Force 10BASE-T port into Link Pass 20 REVPOL Reversed Polarity—Reports 10BASE-T receiver wiring error 10 DAPC Disable Auto Polarity Correction—Detection remains active 08 LRT Low Receive Threshold—Extended distance capability 04 ASEL Auto Select—Select 10BASE-T port when active, otherwise AUI 02 RWAKE Remote Wake—10BASE-T, AUI and EADI features active during sleep 01 AWAKE Auto Wake—10BASE-T receive and LNKST active during sleep 16 CHIPID Chip Identification Register LSB—CHIPID [7:0] RO 17 CHIPID Chip Identification Register MSB—CHIPID [15:8] RO 18 IAC Internal Address Configuration 80 ADDRCHG Address Change—Write to PHYADDR or LOGADDR after ENRCV 40 — 20 — 10 — 08 — 04 — 04 PHYADDR Reset Physical Address pointer 02 LOGADDR Reset Logical Address pointer 01 — 19 — Reserved R/W as 0 20 LADRF Logical Address Filter—8 bytes—8 reads or writes—LS Byte first R/W 21 PADR Physical 6 bytes—6 reads or writes—LS Byte first R/W 22 — Reserved R/W as 0 23 — Reserved R/W as 0 24 MPC Missed Packet Counter—Number of receive packets missed RO 25 — Reserved R/W as 0 26 RNTPC Runt Packet Count—Number of runt packets addressed to this node RO 27 RCVCC Receive Collision Count—Number of receive collision frames on network RO 28 — Reserved R/W as 0 29 UTR User Test Register R/W 80 RTRE Reserved Test Register Enable— must be 0 40 RTRD Reserved Test Register Disable 20 RPA Runt Packet Accept 10 FCOLL Force Collision 08 RCVFCSE Receive FCS Enable 06 LOOP Loopback control (2 bits) 00 No loopback 01 External loopback 10 Internal loopback, excludes MENDEC 11 Internal loopback, includes MENDEC 01 — R/W R/W R/W |
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