AM79C940VCW datasheet(60/122 Pages) AMD

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AMD

Am79C940

Bit 0 ASTRP RCV

Auto Strip Receive. ASTRP RCV

enables the automatic pad strip-

ping feature. The pad and FCS

fields will be stripped from re-

ceive frames and not placed in

the FIFO. ASTRP RCV is set by

activation of the

RESET pin or

the SWRST bit.

Receive Frame Status (RCVFS)

(REG ADDR 6)

RCVFS [31–00]

The Receive Frame Status is a single byte location

which must be read by four read cycles to obtain the four

bytes (32-bits) of status associated with each receive

frame. Receive Frame Status can be read using either

the Register Direct or FIFO Direct access modes.

In Register Direct mode, access to the Receive FIFO will

be denied until all four status bytes for the completed

frame have been read from the Receive Frame Status

location. In FIFO Direct mode, the Receive Frame

Status is read through the Receive FIFO location, by

continuing to execute four read cycles after the comple-

tion of packet data (and assertion of

EOF). The Receive

Frame Status can be read using either mode, or a com-

bination of both modes, however each status byte will be

presented only once regardless of access method.

Other register reads and/or writes can be interleaved at

any time, during the Receive Frame Status sequence.

The Receive Frame Status consists of the following four

bytes of information:

RFS0

Receive Message Byte Count

(RCVCNT) [7–0]

RFS1

Receive Status, (RCVSTS) [11–8]

RFS2

Runt Packet Count (RNTPC) [7–0]

RFS3

Receive Collision Count (RCVCC) [7–0]

RFS0—Receive Message Byte Count (RCVCNT)

RCVCNT [7:0]

Bit

Name

Description

Bit 7-0

RCVCNT

The

Receive

Message Byte

[7:0]

Count indicates the number of

whole bytes in the received mes-

sage. If pad bytes were stripped

from

the

received

frame,

RCVCNT indicates the number

of bytes received less the num-

ber of pad bytes and less the

number of FCS bytes. RCVCNT

is 12 bits long. If a late collision is

detected (CLSN set in RCVSTS),

the count is an indication of the

length (in byte times) of the dura-

tion of the receive activity includ-

ing the collision. RCVCNT [10:8]

correspond to bits 3–0 in RFS1 of

the

Receive

Frame

Status.

RCVCNT [11–0] will be invalid

when OFLO is set.

RFS1—Receive Status (RCVSTS)

OFLO CLSN

FRAM

FCS

RCVCNT [10:8]

Bit

Name

Description

Bit 7

OFLO

Overflow flag. Indicates that the

Receive FIFO over flowed due to

the inability of the host/controller

to read data fast enough to keep

pace with the receive serial bit

stream and the latency provided

by the Receive FIFO itself. OFLO

is indicated on the receive frame

that caused the overflow condi-

tion; complete frames in the Re-

ceive FIFO are not affected.

While the Receive FIFO is in the

overflow condition, it ignores ad-

ditional receive data on the net-

work.

The

internal

address

detect logic will continue to oper-

ate and the Missed Packet Count

(MPC in register 24) will be incre-

mented for each packet which

passes

the

address

match

criteria, and complete without

collision.

Bit 6

CLSN

Collision Flag. Indicates that the

receive operation suffered a colli-

sion during reception of the

frame. If CLSN is set, it indicates

that the receive frame suffered a

late collision, since a frame expe-

riencing collision within the slot

time will be automatically deleted

from the RCVFIFO (providing

LLRCV in the Receive Frame

Control register is cleared). Note

that if the LLRCV bit is enabled,

the late collision threshold is ef-

fectively moved from the normal

64-byte (512-bit) level to the

12-byte (96-bit) level. Runt pack-

ets suffering a collision will be

flushed from the RCVFIFO re-

gardless of the state of the RPA

bit (User Test Register). CLSN

will not be set if OFLO is set.

Bit 5

FRAM

Framing Error flag. Indicates that

the received frame contained a

non-integer multiple of bytes and

an FCS error. If there was no

FCS error then FRAM will not be

set. FRAM is not valid during in-

ternal loopback. FRAM will not

be set if OFLO is set.

Bit 4

FCS

FCS Error flag. Indicates that

there is an FCS error in the

frame. The receive FCS is com-

puted and checked normally

when ASTRP RCV = 1, but is not

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