AM79C940VCW datasheet(61/122 Pages) AMD

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AMD

Am79C940

passed to the host. FCS will not

be set if OFLO is set.

Bit 3–0 RCVCNT

The

Receive

Message

Byte

[11:8]

Count indicates the number of

whole bytes in the received mes-

sage from the network. RCVCNT

is 12 bits long, and valid (accu-

rate) only when there are no er-

rors reported in the Receive

Status (RCVSTS). If a late colli-

sion is detected (CLSN set in

RCVSTS), the count is an indica-

tion of the length (in byte times) of

the duration of the receive activ-

ity

including

the

collision.

RCVCNT [7:0] correspond to bits

7–0 in RFS0 of the Receive

Frame Status. RCVCNT [11–0}

will be invalid when OFLO is set.

RFS2—Runt Packet Count (RNTPC)

RNTPC [7–0]

Bit

Name

Description

Bit 7–0

RNTPC

The Runt Packet Count indicates

[7–0]

the number of runt packets re-

ceived, addressed to this node,

since the last successfully re-

ceived packet. The value does

not roll over after 255 runt pack-

ets have been detected, and will

remain frozen at the maximum

count.

RFS3—Receive Collision Count (RCVCC)

RCVCC [7–0]

Bit

Name

Description

Bit 7–0 RCVCC

The Receive Collision Count in-

[7–0]

dicates the number of collisions

detected on the network since

the last successfully received

packet. The value does not roll

over after 255 collisions have

been detected, and will remain

frozen at the maximum count.

FIFO Frame Count (FIFOFC)

(REG ADDR 7)

RCVFC[3–0]

XMTFC[3–0]

Bit

Name

Description

Bit 7–4

RCVFC

Receive Frame Count. The (read

[3–0]

only) count of the frames in the

Receive

FIFO.

frame

counted when the last byte is put

in the FIFO. The counter is

decremented when the last byte

of the frame is read. If the

RCVFC reaches its maximum

value of 15, additional receive

frames will be ignored, and the

Missed Packet Count (MPC) reg-

ister will be incremented for

frames which match the internal

address(es) of the MACE device.

Bit 3–0 XMTFC

Transmit

Frame

Count. The

[3–0]

(read only) count of the frames in

the Transmit FIFO. A frame is

counted when the last byte is put

in the FIFO. The counter is

decremented when XMTSV (in

the Transmit Frame Status and

Poll Register) is set and the

Transmit Frame Status read ac-

cess is performed.

Interrupt Register (IR)

(REG ADDR 8)

All status bits are set upon occurrence of an event and

cleared when read. The resister is read only. In addition

all status bits are cleared by hardware or software reset.

Bit assignments for the register are as follows:

JAB

CERR RCVCCO RNTPCO

MPCO

RCVINT

BABL

XMTINT

Bit

Name

Description

Bit 7

JAB

Jabber Error. JAB indicates that

the MACE device attempted to

transmit for an excessive time

period (20–150 ms), when using

either

the

DAI

port

the

10BASE-T port. If the internal

jabber timer expires during trans-

mission, the transmit bit stream

will be interrupted, until the inter-

nal transmission ceases and the

unjab timer (0.5 s

±0.25 s) ex-

pires. The jabber function will be

disabled, and JAB will not be

set, regardless of transmission

length, when either the AUI or

GPSI ports have been selected.

JAB is READ/CLEAR only, and is

set by the MACE device and re-

set when read. Writing has no ef-

fect.

also

cleared

activation of the

RESET pin or

SWRST bit.

Bit 6

BABL

Babble Error. BABL is the trans-

mitter time-out error. It indicates

that the transmitter has been on

the channel longer than the time

required to send the maximum

packet. It will be set after 1519

bytes (or greater) have been

transmitted. The MACE device

will continue to transmit until the

current packet transmission is

over. The

INTR pin will be acti-

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