AM79C940VCW datasheet(59/122 Pages) AMD

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AMD

Am79C940

Transmit Retry Count (XMTRC)

(REG ADDR 4)

The Transmit Retry Count should be read only in re-

sponse to a hardware interrupt request (

INTR asserted)

when XMTINT is set in the Interrupt Register, or after

XMTSV is set in the Poll Register.The register should be

read before the Transmit Frame Status register. Read-

ing the Transmit Frame Status with XMTSV set will

cause the XMTRC value to be reset. This register is

read only.

EXDEF

RES

XMTRC[3–0]

RES

Bit

Name

Description

Bit 3-0

EXDEF

Excessive Defer. The EXDEF bit

will be set if a transmit frame

waited for an excessive period

for transmission. An excessive

defer time is defined in accor-

dance with the following (from

page 34, section 5.2.4.1 of IEEE

Std 802.3h–1990 Layer Manage-

ment):maxDeferTime = {2 x (max

frame size x 8)} bits where

maxFrameSize = 1518 bytes

(from page 68, section 4.4.2.1 of

ANSI/IEEE

Std

802.3–1990).

So, the maxDeferTime = 24288

bits = 214+ 212 + 211+ 210 + 29 +27

+26 +25

Bit 6–4 RES

Reserved. Read as zeroes. Al-

ways write as zeroes.

Bit 3–0 XMTRC

Transmit Retry Count. Contains

[3–0]

the count of the number of retry

attempts made by the MACE de-

vice to transmit the current trans-

mit packet. The value of the

counter will be zero if the first

transmission attempt was suc-

cessful, and a maximum of 15 if

all retry attempts were utilized.

RTRY will be set in Transmit

Frame Status if all 16 attempts

were unsuccessful.

Receive Frame Control (RCVFC)

(REG ADDR 5)

RES

LLRCV

M/R

RES

ASTRPRCV

RES

Bit

Name

Description

Bit 7–4 RES

Reserved. Read as zeroes. Al-

ways write as zeroes.

Bit 3

LLRCV

Low Latency Receive. A pro-

grammable option to allow ac-

cess to the Receive FIFO before

the 64-byte threshold has been

reached. When set, data can be

read from the RCVFIFO once a

low threshold (12-bytes after

SFD plus synchronization) has

been

exceeded,

causing

RDTREQ

asserted.

RDTREQ will remain asserted as

long as one read cycle can be

performed

the

RCVFIFO

(identical to the burst mode).

Indication of a valid read cycle

from the RCVFIFO will return

DTV asserted. Reading the

RCVFIFO before data is avail-

able, or while waiting for addi-

tional data once a packet is in

progress will not cause the

RCVFIFO to underflow, and will

be indicated by

DTV being inva-

lid. The MACE device will no

longer be able to reject runts in

this mode, this responsibility is

transferred to the host system. In

the case of a collided packet

(normal slot time collision or late

collision), the MACE device will

abort the reception, and return

the RCVFS. Note that all colli-

sions in this mode will appear as

late collisions and be reported by

the CLSN bit in the Receive

Status (RCVSTS) byte.

If the host does not keep up with

the incoming receive data, nor-

mal RCVFIFO overflow recovery

is provided.

Bit 2

Match/Reject. The Match/Reject

option sets the criteria for the Ex-

ternal Address Detection Inter-

face. If set, the

EAM/R pin is

configured as External Address

Match, and is used to signal the

acceptance of a receive frame to

the MACE device. If cleared, the

pin functions as External Ad-

dress Reject and is used to flush

unwanted packets from the Re-

ceive FIFO prior to the first asser-

tion of

RDTREQ. M/R is cleared

by activation of the

RESET pin or

SWRST bit. When the EADI fea-

ture is disabled, the

EAM/R pin

must be tied active (low) and all

normal receive address recogni-

tion configurations are supported

(physical, logical and promiscu-

ous). See the section “External

Address Detection Interface” for

additional details.

Bit 1

RES

Reserved. Read as zero. Always

write as zero.

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