AM79C940VCW datasheet(66/122 Pages) AMD

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AMD

Am79C940

TDTREQ will be asserted identi-

cally in both normal and burst

modes, when there is sufficient

space in the XMTFIFO to allow

the specified number of write

cycles to occur (programmed by

the XMTFW bits).

Cleared by activation of the

RESET pin or SWRST bit.

Bit 0

RCVBRST

Receive Burst. When set, the re-

ceive burst mode is selected. The

behavior of the Receive FIFO low

watermark, and hence the de-

assertion of

RDTREQ, will be

modified.

RDTREQ will de-assert

when there are only 2-bytes of

data available in the RCVFIFO

(so that a full word read can still

occur).

RDTREQ will be asserted identi-

cally in both normal and burst

modes, when a minimum of

64-bytes have been received for

a new frame (or a runt packet has

been received and RPA is set).

Once the 64-byte limit has been

exceeded,

RDTREQ will be as-

serted providing there is suffi-

cient data in the RCVFIFO to

exceed the threshold, as pro-

grammed by the RCVFW bits.

Cleared by activation of the

RESET pin or SWRST bit.

MAC Configuration

Control (MACCC)

(REG ADDR 13)

This register programs the transmit and receive opera-

tion and behavior of the internal MAC engine. All bits

within the MAC Configuration Control register are

cleared upon hardware or software reset. Bit assign-

ments are as follows:

PROM DXMT2PD EMBA RES DRCVPA DRCVBC ENXMT ENRCV

Bit

Name

Description

Bit 7

PROM

Promiscuous. When PROM is

set all incoming frames are re-

ceived regardless of the destina-

tion address. PROM is cleared

by activation of the

RESET pin or

SWRST bit.

Bit 6

DXMT2PD

Disable Transmit Two Part De-

ferral. When set, disables the

transmit two part deferral option.

DXMT2PD is cleared by activa-

tion of the

RESET pin or SWRST

bit.

Bit 5

EMBA

Enable Modified Back-off Algo-

rithm. When set, enables the

modified

backoff

algorithm.

EMBA is cleared by activation of

the

RESET pin or SWRST bit.

Bit 4

RES

Reserved. Read as zeroes. Al-

ways write as zeroes.

Bit 3

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the MACE device will be

disabled. Packets addressed to

the nodes individual physical ad-

dress will not be recognized (al-

though

the

packet

may

accepted

the

EADI

mechanism).

DRCVPA

cleared by activation of the

RESET pin or SWRST bit.

Bit 2

DRCVBC

Disable

Receive

Broadcast.

When set, disables the MACE

device from responding to broad-

cast messages. Used for proto-

cols

that

not

support

broadcast addressing, except as

a function of multicast. DRCVBC

is cleared by activation of the

RE-

SET pin or SWRST bit (broad-

cast messages will be received).

Bit 1

ENXMT

Enable

Transmit.

Setting

ENXMT = 1 enables transmis-

sion. With ENXMT = 0, no trans-

mission will occur. If ENXMT is

written as 0 during frame trans-

mission, a packet transmission

which is incomplete will have a

guaranteed CRC violation ap-

pended

before

the

internal

Transmit FIFO is cleared. No

subsequent attempts to load the

FIFO should be made until

ENXMT is set and

TDTREQ is

asserted. ENXMT is cleared by

activation of the

RESET pin or

SWRST bit.

Bit 0

ENRCV

Enable Receive. Setting ENRCV

= 1 enables reception of frames.

With ENRCV = 0, no frames will

be received from the network into

the internal FIFO. When ENRCV

is written as 0, any receive frame

currently in progress will be com-

pleted (and valid data contained

in the RCVFIFO can be read by

the host) and the MACE device

will enter the monitoring state for

missed packets. Note that clear-

ing the ENRCV bit disables the

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