AM79C940VCW datasheet(54/122 Pages) AMD

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AMD

Am79C940

Receive frames which have a length field of 46 bytes or

greater will be passed to the host unmodified.

Since any valid Ethernet Type field value will always be

greater than a normal 802.3 Length field, the MACE de-

vice will not attempt to strip valid Ethernet frames.

Note that for some network protocols, the value passed

in the Ethernet Type and/or 802.3 Length field is not

compliant with either standard and may cause

problems.

The diagram below shows the byte/bit ordering of the re-

ceived length field for an 802.3 compatible frame format.

16907A-013A

Preamble

1010....1010

SYNCH

10101011

Dest.

ADDR.

SRCE.

ADDR.

Length

LLC

DATA

Pad

FCS

Bits

Bytes

46-1500

Bytes

Most

Significant

Byte

Least

Significant

Byte

Bit

Start of Packet

at Time= 0

Increasing Time

Bit

45-0

Bytes

1-1500

Bytes

16235C-9

802.3 Packet and Length Field Transmission Order

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the MACE device. Note that if

the Automatic Pad Stripping feature is enabled, the re-

ceived FCS will be verified against the value computed

for the incoming bit stream including pad characters, but

it will not be passed through the Receive FIFO to the

host. If an FCS error is detected, this will be reported by

the FCS bit (bit 4) in the Receive Frame Status.

Receive Status Information

The

EOF indication signals that the last byte/word of

data has been passed from the FIFO for the specific

frame. This will be accompanied by a RCVINT indication

in the the Interrupt Register signaling that the Receive

Frame Status has been updated, and must be read. The

Receive Frame Status is a single location which must be

read four times to allow the four bytes of status informa-

tion associated with each frame to be read. Further data

read operations from the Receive FIFO using the Regis-

ter Address mode, will be ignored by the MACE device

(indicated by the MACE chip not returning

DTV) until all

four bytes of the Receive Frame Status have been read.

Alternatively, the FIFO Direct access mode may be

used to read the Receive Frame Status through the Re-

ceive FIFO. In either case, the 4-byte total must be read

before additional receive data can be read from the Re-

ceive FIFO. However, the

RDTREQ indication will con-

tinue to reflect the state of the Receive FIFO as normal,

regardless of whether the Receive Frame Status has

been read.

DTV will not be returned when a read opera-

tion is performed on the Receive Frame Status location

and no valid status is present or ready.

Note that the Receive Frame Status can be read using

either the Register Address or FIFO Direct modes. For

additional details, see the section

Receive FIFO Read.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinct categories; those which are the result of normal

network operation, and those which occur due to abnor-

mal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the MACE device are basically colli-

sions within the slot time and automatic runt packet de-

letion. The MACE device will ensure that any receive

packet which experiences a collision within 512 bit times

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