AM79C940VCW datasheet(24/122 Pages) AMD

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AMD

Am79C940

EAM/R

External Address Match/Reject

(Input)

The incoming frame will be received dependent on the

receive operational mode of the MACE device, and the

polarity of the

EAM/R pin. The EAM/R pin function is

programmed by use of the M/

R bit in the Receive Frame

Control register. If the bit is set, the pin is configured as

EAM. If the bit is reset, the pin is configured as EAR.

EAM/R can be asserted during packet reception to ac-

cept or reject packets based on an external address

comparison.

SRDCLK

Serial Receive Data Clock

(Input/Output)

The Serial Receive Data (SRD) output is synchronous

to SRDCLK running at the 10MHz receive data clock fre-

quency. The pin is configured as an input, only when the

GPSI port is selected. Note that when the 10BASE-T

port is selected, transition on SRDCLK will only occur

during receive activity. When the AUI or DAI port is se-

lected, transition on SRDCLK will occur during both

transmit and receive activity.

SRD Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

SRD Output

10BASE-T

SRD Output

DAI Port

SRD Output

GPSI

SRD Output

Status Disabled

High Impedance

Note: PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

SRDCLK Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

SRDCLK Output

10BASE-T

SRDCLK Output

DAI Port

SRDCLK Output

GPSI

SRDCLK Input

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

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