AM79C940VCW datasheet(67/122 Pages) AMD

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AMD

Am79C940

assertion of

RDTREQ. If ENRCV

is cleared during receive activity

and remains cleared for a long

time and if the tail end of the re-

ceive frame currently in progress

is longer than the amount of

space available in the Receive

FIFO, Receive FIFO overflow will

occur.

However,

even

with

RDTREQ deasserted, if there is

valid data in the Receive FIFO to

be read, successful slave reads

to the Receive FIFO can be exe-

cuted (indicated by valid

DTV). It

is the host’s responsibility to

avoid

the

overflow

situation.

ENRCV is cleared by activation

of the

RESET pin or SWRST bit.

PLS Configuration

Control (PLSCC)

(REG ADDR 14)

All bits within the PLS Configuration Control register are

cleared upon a hardware or software reset. Bit assign-

ments are as follows:

RES

XMTSEL

PORTSEL [1–0]

ENPLSIO

Bit

Name

Description

Bit 7–4 RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 3

XMTSEL

Transmit Mode Select. XMTSEL

provides control over the AUI

DO+ and DO– operation while

the MACE device is not transmit-

ting. With XMTSEL = 0, DO+ and

DO will be equal during transmit

idle state, providing zero differ-

ential to operate transformer

coupled loads. The turn off and

return to zero delays are con-

trolled internally. With XMTSEL =

1, DO+ is positive with respect to

DO during the transmit idle state .

Bit 2–1 PORTSEL

Port Select. PORTSEL is used to

[1–0]

select

between

the

AUI,

10BASE-T, DAI or GPSI ports of

the MACE device. PORTSEL is

cleared by hardware or software

reset. PORTSEL will determine

which of the interfaces is used

during

normal

operation,

tested when utilizing the loop-

back options (LOOP [1–0]) in the

User Test Register. Note that the

PORTSEL [1–0] programming

will be overridden if the ASEL bit

in the PHY Configuration Control

PORTSEL Interface Definition

PORTSEL

Active

[1–0]

Interface

DXCVR Pin

AUI

LOW

10BASE-T

HIGH

DAI Port

HIGH

GPSI

LOW

Bit 0

ENPLSIO

Enable PLS I/O. ENPLSIO is

used to enable the optional I/O

functions from the PLS function.

The following pins are affected

by the ENPLSIO bit: RXCRS,

RXDAT,

TXEN,

TXDAT+,

TXDAT–,

CLSN,

STDCLK,

SRDCLK and SRD. Note that if

an external SIA is being utilized

via the GPSI, PORTSEL [1–0] =

11 must be programmed before

ENPLSIO is set, to avoid conten-

tion of clock, data and/or carrier

indicator signals.

PHY Configuration

Control (PHYCC)

(REG ADDR 15)

All bits within the PHY Configuration Control register

with the exception of LNKFL, are cleared by hardware or

software reset. Bit assignments are as follows:

LNKFL DLNKTST REVPOL DAPC

LRT

ASEL

RWAKE

AWAKE

Bit

Name

Description

Bit 7

LNKFL

Link Fail. Reports the link integ-

rity of the 10BASE-T receiver.

When the link test function is en-

abled (DLNKTST = 0), the ab-

sence of link beat pulses on the

RXD

± pair will cause the inte-

grated 10BASE-T transceiver to

go into the link fail state. In the

link fail state, data transmission,

data reception, data loopback

and the collision detection func-

tions are disabled, and remain

disabled until valid data or >5

consecutive link pulses appear

on the RXD

± pair. During link fail,

the LNKFL bit will be set and the

LNKST pin should be externally

pulled HIGH. When the link is

identified

functional,

the

LNKFL bit will be cleared and the

LNKST pin is driven LOW, which

is capable of directly driving a

Link OK LED. In order to inter-

operate with systems which do

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