AM79C940VCW datasheet(30/122 Pages) AMD

30 / 122 page

AMD

Am79C940

The Transmit FIFO data will not be overwritten until at

least 512 data bits have been transmitted onto the net-

work. If a collision occurs within the slot time (512 bit

time) window, the MACE device will generate a jam se-

quence (a 32-bit all zeroes pattern) before ceasing the

transmission. The Transmit FIFO will be reset to point at

the start of the transmit data field, and the message will

be retried after the random back-off interval has expired.

DETAILED FUNCTIONS

Block Level Description

The following sections describe the major sub-blocks of

and the external interfaces to the MACE device.

Bus Interface Unit (BIU)

The BIU performs the interface between the host or sys-

tem bus and the Transmit and Receive FIFOs, as well as

all chip control and status registers. The BIU can be con-

figured to accept data presented in either little-endian or

big endian format, minimizing the external logic required

to access the MACE device internal FIFOs and regis-

ters. In addition, the BIU directly supports 8-bit transfers

and incorporates features to simplify interfacing to 32-bit

systems using external latches.

Externally, the FIFOs appear as two independent regis-

ters located at individual addresses. The remainder of

the internal registers occupy 30 additional consecutive

addresses, and appear as 8-bits wide.

BIU to FIFO Data Path

The BIU operates assuming that the 16-bit data path to/

from the internal FIFOs is configured as two independ-

ent byte paths, activated by the Byte Enable signals

BE0

and

BE1.

BE0 and BE1 are only used during accesses to the

16-bit wide Transmit and Receive FIFOs. After hard-

ware or software reset, the BSWP bit will be cleared.

FIFO accesses to the MACE device will operate assum-

ing an Intel 80x86 type memory convention (most sig-

nificant byte of a word stored in the higher addressed

byte). Word data transfers to/from the FIFOs over the

DBUS15–0 lines will have the least significant byte lo-

cated on DBUS7–0 (activated by

BE0) and the most sig-

nificant byte located on DBUS15–8 (activated by

BE1).

FIFO data can be read or written using either byte and/or

word operations.

If byte operation is required, read/write transfers can be

performed on either the upper or lower data bus by as-

serting the appropriate byte enable. For instance with

BSWP = 0, reading from or writing to DBUS15–8 is ac-

complished by asserting

BE1, and allows the data

stream to be read from or written to the appropriate

FIFO in byte order (byte 0, byte 1,....byte n). It is equally

valid to read or write the data stream using DBUS7–0

and by asserting

BE0. For BSWP = 1, reading from or

writing to DBUS15–8 is accomplished by asserting

BE0,

and allows the byte stream to be transferred in byte

order.

When word operations are required, BSWP ensures

that the byte ordering of the target memory is compatible

with the 802.3 requirement to send/receive the data

stream in byte ascending order. With BSWP = 0, the

data transferred to/from the FIFO assumes that byte n

will be on DBUS7–0 (activated by

BE0) and byte n+1 will

be on DBUS15–8 (activated by

BE1). With BSWP = 1,

the data transferred to/from the FIFO assumes that byte

n will be presented on DBUS15–8 (activated by

BE0),

and byte n+1 will be on DBUS7–0 (activated by

BE1).

There are some additional special cases to the above

generalized rules, which are as follows:

(a) When performing byte read operations, both halves

of the data bus are driven with identical data, effec-

tively allowing the user to arbitrarily read from either

the upper or lower data bus, when only one of the

byte enables is activated.

(b) When byte write operations are performed, the

Transmit FIFO latency is affected. See the FIFO

Sub-System section for additional details.

receive frame (

EOF is asserted), and the message

contained an odd number of bytes but the host re-

quested a word operation by asserting both

BE0

and

BE1, then the MACE device will present one

valid and one non-valid byte on the data bus. The

placement of valid data for the data byte is depend-

ent on the target memory architecture. Regardless

of BSWP, the single valid byte will be read from the

BE0 memory bank. If BSWP = 0, BE0 corresponds

to DBUS7–0; if BSWP = 1,

BE0 corresponds to

DBUS15–8.

(d) If a byte read is performed when the last data byte is

read for a receive frame (when the MACE device

activates the

EOF signal), then the same byte will

be presented on both the upper and lower byte of

the data bus, regardless of which byte enable was

activated (as is the case for all byte read opera-

tions).

(e) When writing the last byte in a transmit message to

the Transmit FIFO, the portion of the data bus that

the last byte is transferred over is irrelevant, provid-

ing the appropriate byte enable is used. For

BSWP = 0, data can be presented on DBUS7–0 us-

ing

BE0 or DBUS15–8 using BE1. For BSWP = 1,

data can be presented on DBUS7–0 using

BE1 or

DBUS15–8 using

BE0.

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