AM79C940VCW datasheet(50/122 Pages) AMD

50 / 122 page

AMD

Am79C940

Preamble

1010....1010

SYNCH

Dest

Addr

Srce

Addr

Type

Data

FCS

Bits

Bytes

46—1500

Bytes

16235C-8

Ethernet Format Data Frame

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS (Dis-

able Transmit FCS) when the

EOF is asserted indicating

the last byte/word of data for the transmit frame is being

written to the FIFO. The action of writing the last data

byte/word of the transmit frame, latches the current con-

tents of the Transmit Frame Control register, and there-

fore determines the programming of DXMTFCS for the

transmit frame. When DXMTFCS = 0 the transmitter will

generate and append the FCS to the transmitted frame.

If the automatic padding feature is invoked (APAD XMT

in Transmit Frame Control), the FCS will be appended

regardless of the state of DXMTFCS. Note that the cal-

culated FCS is transmitted most significant bit first. The

default value of DXMTFCS is 0 after hardware or soft-

ware reset.

Transmit Status Information

Although multiple transmit frames can be queued in the

Transmit FIFO, the MACE device will not permit loss of

Transmit Frame Status information. The Transmit

Frame Status and Transmit Retry Count can only be

buffered internally for a maximum of two frames. The

MACE device will therefore not commence a third trans-

mit frame, until the status from the first frame is read.

Once the Transmit Retry Count and Transmit Frame

Status for the first transmit packet is read, the MACE

device will autonomously begin the next transmit frame,

provided that a transmit frame is pending, the XMTSP

threshold has been exceeded (or the XMTFIFO is full),

the network medium is free, and the IPG time has

elapsed.

Indication of valid Transmit Frame Status can be ob-

tained by servicing the hardware interrupt and testing

the XMTINT bit in the Interrupt Register, or by polling the

XMTSV bit in the Poll register if a continuous polling

mechanism is required. If the Transmit Retry Count data

is required (for loading, diagnostic, or management in-

formation), XMTRC must be read prior to XMTFS.

Reading the XMTFS register when the XMTSV bit is set

will clear both the XMTRC and XMTFS values.

Transmit Exception Conditions

Exception conditions for frame transmission fall into two

distinct categories; those which are the result of normal

network operation and those which occur due to abnor-

mal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the MACE device are:

(a) Collisions within the slot time with automatic retry

(b) Deletion of packets due to excessive transmission

attempts.

(a) The MACE device will ensure that collisions which

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with no

host intervention. The Transmit FIFO ensures this by

guaranteeing that data contained within the Transmit

FIFO will not be overwritten until at least 64 bytes (512

bits) of data have been successfully transmitted onto the

network. This criteria will be met, regardless of whether

the transmit frame was the first (or only) frame in the

Transmit FIFO, or if the transmit frame was queued

pending completion of the preceding frame.

(b) If 16 total attempts (initial attempt plus 15 retries)

have been made to transmit the frame, the MACE de-

vice will abandon the transmit process for the particular

frame, de-assert the

TDTREQ pin, report a Retry Error

(RTRY) in the Transmit Frame Status, and set the

XMTINT bit in the Interrupt Register, causing activation

of the external

INTR pin providing the interrupt is

unmasked.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the RTRY error is still in the host memory (i.e.,

when XMTFC = 0). This XMTFC read should be re-

quested before the Transmit Frame Status read since

reading the XMTFS would cause the XMTFC to decre-

ment. If the tail end of the frame is indeed still in the host

memory, the host is responsible for ensuring that the tail

end of the frame does not get written into the FIFO and

does not get transmitted as a whole frame. It is recom-

mended that the host clear the tail end of the frame from

the host memory before requesting the XMTFS read so

that after the XMTFS read, when MACE device re-as-

serts

TDTREQ, the tail end of the frame does not get

written into the FIFO. The Transmit Frame Status read

will indicate that the RTRY error occurred. The read op-

eration on the Transmit Frame Status will update the

FIFO read and write pointers. If no

End-of-Frame write

(

EOF pin assertion) had occurred during the FIFO write

sequence, the entire transmit path will be reset (which

will update the Transmit FIFO watermark with the

AM79C940VCW Datenblatt(PDF) 50 Page - Advanced Micro Devices

AM79C940VCW Datenblatt(HTML) 50 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL