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AM79C940VCW Datenblatt(PDF) 93 Page - Advanced Micro Devices

Teilenummer AM79C940VCW
Bauteilbeschribung  Media Access Controller for Ethernet (MACE)
PDF  122 Pages
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Hersteller  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C940VCW Datenblatt(HTML) 93 Page - Advanced Micro Devices

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AMD
93
Am79C940
AC CHARACTERISTICS (continued)
Parameter
No.
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
AUI Timing
53
tDOTD
XTAL1 (externally driven) to
DO
± output
100
54
tDOTR
DO
± rise time (10% to 90%)
2.5
5.0
55
tDOTF
DO
± fall time (10% to 90%)
2.5
5.0
56
tDOETM
DO
± rise and fall mismatch
1
57
tDOETD
DO
± End of Transmit Delimiter
200
375
58
tPWRDI
DI
± pulse width to reject
|input| > |VASQ|15
59
tPWODI
DI
± pulse width to turn on
|input| > |VASQ|45
internal DI carrier sense
60
tPWMDI
DI
± pulse width to maintain
|input| > |VASQ|
45
136
internal DI carrier sense on
61
tPWKDI
DI
± pulse width to turn internal
|input| > |VASQ|
200
DI carier sense off
62
tPWRCI
CI
± pulse width to reject
|input| > |VASQ|10
63
tPWOCI
CI
± pulse width to turn on
|input| > |VASQ|26
internal SQE sense
64
tPWMCI
CI
± pulse width to maintain
|input| > |VASQ|26
90
internal SQE sense on
65
tPWKCI
CI
± pulse width to turn internal
|input| > |VASQ|
160
SQE sense off
66
tSQED
CI
± SQE Test delay from
|input| > |VASQ|
O
± inactive
67
tSQEL
CI
± SQE Test length
|input| > |VASQ|
79
tCLSHI
CLSN high time
tSTDC+30
80
tTXH
TXEN or DO
± hold time from
|input| > |VASQ|
32*tSTDC
96*tSTDC
CLSN
↑
DAI Port Timing
70
tTXEND
STDCLK
↑ delay to TXEN↓
CL = 50 pF
70
72
tTXDD
STDCLK
↑ delay to TXDAT±
CL = 50 pF
70
change
80
tXH
TXEN or TXDAT
± hold time
32*tSTDC
96*tSTDC
from CLSN
↑
95
tDOTF
Mismatch in STDCLK
≠ to TXEN↓
15
and TXDAT
± change
96
tTXDTR
TXDAT
± rise time
See Note 1
5
97
tTXDTF
TXDAT
± fall time
See Note 1
5
98
tTXDTM
TXDAT
± rise and fall mismatch
See Note 1
1
99
tTXENETD
TXEN End of Transmit Delimiter
250
350
100
tFRXDD
First RXDAT
↓ delay to RXCRS↑
100
101
tLRXDD
Last RXDAT
≠ delay to RXCRS↓
120
102
tCRSCLSD
RXCRS
↑ delay to CLSN↑
100
(
TXEN = 0)



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