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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AM79C940VCW Datenblatt(PDF) 92 Page - Advanced Micro Devices |
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AM79C940VCW Datenblatt(HTML) 92 Page - Advanced Micro Devices |
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92 / 122 page  AMD 92 Am79C940 AC CHARACTERISTICS Parameter No. Symbol Parameter Description Test Conditions Min (ns) Max (ns) Clock and Reset Timing 1tSCLK SCLK period 40 1000 2tSCLKL SCLK LOW pulse width 0.4*tSCLK 0.6*tSCLK 3tSCLKH SCLK HIGH pulse width 0.4*tSCLK 0.6*tSCLK 4tSCLKR SCLK rise time 5 5tSCLKF SCLK fall time 5 6tRST RESET pulse width 15*tSCLK 7tBT Network Bit Time (BT) 99 101 =2*tX1 or tSTDC) Internal MENDEC Clock Timing 9tX1 XTAL1 period 49.995 50.005 11 tX1H XTAL1 HIGH pulse width 20 12 tX1L XTAL1 LOW pulse width 20 13 tX1R XTAL1 rise time 5 14 tX1F XTAL1 fall time 5 BIU Timing (Note 1) 31 tADDS Address valid setup to SCLK ↓ 9 32 tADDH Address valid hold after SCLK ↓ 2 33 tSLVS CS or FDS and TC, BE1–0, R/ W setup to SCLK ↓ 9 34 tSLVH CS or FDS and TC, BE1–0, R/ W hold after SCLK ↓ 2 35 tDATD Data out valid delay from SCLK ↓ CL = 100 pF (Note 2) 32 36 tDATH Data out valid hold after SCLK ↓ 6 37 tDTVD DTV valid delay from SCLK ↓ CL = 100 pF (Note 2) 32 38 tDTVH DTV valid hold after SCLK ↓ 6 39 tEOFD EOF valid delay from SCLK ↓ CL = 100 pF (Note 2) 32 40 tEOFH EOF output valid hold after SCLK ↓ 6 41 tCSIS CS inactive prior to SCLK ↓ 9 42 tEOFS EOF input valid setup to SCLK ↓ 9 43 tEOFH EOF input valid hold after SCLK ↓ 2 44 tRDTD RDTREQ valid delay from SCLK ↓ CL = 100 pF (Note 2) 32 45 tRDTH RDTREQ valid hold after SCLK ↓ 6 46 tTDTD TDTREQ valid delay from SCLK ↓ CL = 100 pF (Note 2) 32 47 tTDTH TDTREQ valid hold after SCLK ↓ 6 48 tDATS Data in valid setup to SCLK ↓ 9 49 tDATIH Data in valid setup after SCLK ↓ 2 50 tDATE Data output enable delay from 0 SCLK ↓ (Note 3) 51 tDATD Data output disable delay from 25 SCLK ↓ (Notes 3, 4) Notes: 1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge of SCLK (SCLK ↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK (SCLK↑). 2. Tested with CL set at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay vs. Load Chart. 3. Guaranteed by design—not tested. 4. tDATD is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead. |
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