MCP3918 datasheet(23/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 23

MCP3918

4.0

TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this data sheet. The following terms are

defined:

• MCLK – Master Clock

• AMCLK – Analog Master Clock

• DMCLK – Digital Master Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

• Offset Error

• Gain Error

• Integral Non-Linearity Error

• Signal-to-Noise Ratio (SNR)

• Signal-to-Noise and Distortion Ratio (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3918 Delta-Sigma Architecture

• Idle Tones

• Dithering

• PSRR

• CMRR

• ADC Reset Mode

• Hard Reset Mode (RESET = 0)

• ADC Shutdown Mode

• Full Shutdown Mode

4.1

MCLK – Master Clock

This is the fastest clock present on the device. This is

the frequency of the crystal placed at the OSC1/OSC2

inputs when CLKEXT = 0 or the frequency of the clock

input at the OSC1/CLKI when CLKEXT = 1. In the 2-

Wire mode, this is the frequency present at the SCK

input pin. See Figure 4-1.

4.2

AMCLK – Analog Master Clock

AMCLK is the clock frequency that is present on the

analog portion of the device, after prescaling has

occurred via the PRE<1:0> bits in the CONFIG0

includes the PGA and one delta-sigma modulator.

EQUATION 4-1:

FIGURE 4-1:

Clock Sub-Circuitry.

4.3

DMCLK – Digital Master Clock

This is the clock frequency that is present on the digital

portion of the device, after prescaling and division by

four (Equation 4-2). This is also the sampling

frequency, which is the rate at which the modulator

outputs are refreshed. Each period of this clock

corresponds to one sample and one modulator output.

See Figure 4-1.

EQUATION 4-2:

4.4

DRCLK – Data Rate Clock

This is the output data rate, i.e. the rate at which the

ADC outputs new data. Each new data is signaled by a

Data Ready pulse on the Data Ready pin.

This data rate is dependent on the OSR and the

prescaler with the formula in Equation 4-3.

EQUATION 4-3:

TABLE 4-1:

MCP3918 OVERSAMPLING

RATIO SETTINGS

CONFIG0

Analog Master Clock

Prescale

PRE<1:0>

AMCLK = MCLK/1 (default)

AMCLK = MCLK/2

AMCLK = MCLK/4

AMCLK = MCLK/8

AMCLK

MCLK

PRESCALE

-------------------------------

Xtal Oscillator

MCLK

OSC1

OSC2

Multiplexer

OUT

1/PRESCALE

1/4

1/OSR

AMCLK

DMCLK

DRCLK

Clock Divider

OSR<2:0>

PRE<1:0>

CLKEXT

Multiplexer

OUT

MODE

SCK

DMCLK

AMCLK

---------------------

MCLK

PRESCALE



----------------------------------------

DRC LK

DMC LK

OSR

----------------------

AMCLK

4OSR



---------------------

MCLK

OSR

PRESCALE



-----------------------------------------------------------

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