MCP3918 datasheet(28/88 Pages) MICROCHIP

28 / 88 page

MCP3918

DS20005287A-page 28

 2014 Microchip Technology Inc.

4.19

Hard Reset Mode (RESET = 0)

This mode is only available during a POR or when the

RESET pin is pulled low in the SPI mode. The RESET

pin logic-low state places the device in Hard Reset

mode. In this mode, all internal registers are reset to

their default state. In the 2-Wire Interface mode, the

RESET pin functionality is not available and the user

must use a watchdog timer reset to be able to fully reset

the part (see Section 7.4 “Watchdog Timer Reset,

Resetting the Part when in 2-Wire Mode”

The DC biases for the analog blocks are still active, i.e.

the MCP3918 is ready to convert. However, this pin

clears all conversion data in the ADC. The

comparators’ outputs of the ADC are forced to their

Reset state (0011). The sinc filter as well as its double

output buffers are all reset. See serial timing for

minimum pulse low time in Section 1.0 “Electrical

Characteristics”

During

Hard

Reset,

communication with the part is possible. The digital

interface is maintained in a Reset state.

During this state, the clock MCLK can be applied to the

part in order to properly bias the input structures of all

channels. If not applied, large analog input leakage

currents can be observed for highly negative input

signals, and, after removing the Hard Reset state, a

certain start-up time is necessary to properly bias the

input structure. During this delay, the ADC conversions

can be inaccurate.

4.20

ADC Shutdown Mode

ADC Shutdown mode is defined as a state where the

converters and their biases are off, consuming only

leakage current. When the Shutdown bit is reset to ‘0’,

the analog biases will be enabled, as well as the clock

and the digital circuitry. The ADC will give a data ready

after the sinc filter settling time has occurred. However,

since the analog biases are not completely settled at

the beginning of the conversion, the sampling may not

be accurate for about 1 ms (corresponding to the

settling time of the biasing under worst-case

conditions). In order to ensure accuracy, the Data

Ready pulse within the delay of 1 ms + settling time of

the sinc filter should be discarded.

The configuration registers are not modified by the

Shutdown mode. This mode is only available in SPI

mode through programming the SHUTDOWN<1:0>

bits in the CONFIG1 register.

The output data is flushed to all zeros while in ADC

Shutdown mode. While in ADC Shutdown mode, no

Data Ready pulse will be generated by the ADC.

When the ADC exits ADC Shutdown mode, any phase

delay present before Shutdown was entered will still be

present.

If the ADC is in Shutdown mode, the clock is not

distributed to the input structure or to the digital core for

low-power operation. This can potentially cause high

analog input leakage currents at the analog inputs if the

input voltage is highly negative (typically below -0.6V

referred to AGND). Once the ADC is back to normal

operation, the clock is automatically distributed again.

4.21

Full Shutdown Mode

The lowest power consumption can be achieved when

SHUTDOWN<0> = 1, VREFEXT = CLKEXT = 1. This

mode is called Full Shutdown mode, and no analog

circuitry is enabled. In this mode, both AVDD and DVDD

POR monitoring are also disabled, and no clock is

propagated throughout the chip. The ADC is in

Shutdown mode, and the internal voltage reference is

disabled. This mode can only be entered during SPI

mode.

The clock is no longer distributed to the input structure

either. This can potentially cause high analog input

leakage currents at the analog inputs, if the input

voltage is highly negative (typically below -0.6V

referred to AGND).

The only circuit that remains active is the SPI interface,

but this circuit does not induce any static power

consumption. If SCK is idle, the only current

consumption comes from the leakage currents induced

by the transistors and is less than 5 µA on each power

supply.

This mode can be used to power down the chip

completely and to avoid power consumption when

there is no data to convert at the analog inputs. Any

SCK or MCLK edge occurring while in this mode will

induce dynamic power consumption.

Once any of the SHUTDOWN, CLKEXT and VREFEXT

bits returns to ‘0’, the two POR monitoring blocks are

operational, and AVDD and DVDD monitoring can take

place.

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