MCP3918 datasheet(27/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 27

MCP3918

4.15

Dithering

In order to suppress or attenuate the idle tones present

in any delta-sigma ADC, dithering can be applied to the

ADC. Dithering is the process of adding an error to the

ADC feedback loop in order to “decorrelate” the outputs

and “break” the idle tone’s behavior. Usually a random

or pseudo-random generator adds an analog or digital

error to the feedback loop of the delta-sigma ADC in

order to ensure that no tonal behavior can happen at its

outputs. This error is filtered by the feedback loop and

typically has a zero average value, so that the

converter’s static transfer function is not disturbed by

the dithering process. However, the dithering process

slightly increases the noise floor (it adds noise to the

part) while reducing its tonal behavior and thus

improving SFDR and THD. The dithering process

scrambles the idle tones into baseband white noise and

ensures that dynamic specs (SNR, SINAD, THD,

SFDR) are less signal-dependent. The MCP3918

incorporates a proprietary dithering algorithm on the

ADC in order to remove idle tones and improve THD,

which is crucial for power metering applications.

4.16

PSRR

This is the ratio between a change in the power supply

voltage and the ADC output codes. It measures the

influence of the power supply voltage on the ADC

outputs.

The PSRR specification can be DC (the power supply

takes multiple DC values) or AC (the power supply is a

sine wave at a certain frequency with a certain

common-mode). In AC, the amplitude of the sine wave

represents the change in the power supply. It is defined

in Equation 4-10.

EQUATION 4-10:

Where VOUT is the equivalent input voltage that the

output code translates to, with the ADC transfer

function.

In the MCP3918 specification, AVDD varies from 2.7V

to 3.6V, and for AC PSRR a 50/60 Hz sine wave

centered around 3.0V is chosen, with a maximum

amplitude of 300 mV. The PSRR specification is

measured with AVDD =DVDD.

4.17

CMRR

CMRR is the ratio between a change in the

common-mode input voltage and the ADC output

codes. It measures the influence of the common-mode

input voltage on the ADC outputs.

The

CMRR

specification

can

(the

common-mode input voltage takes multiple DC values)

or AC (the common-mode input voltage is a sine wave

at a certain frequency with a certain common-mode). In

AC, the amplitude of the sine wave represents the

change in the power supply. It is defined in Equation 4-

11.

EQUATION 4-11:

Where VCM = (CH0+ + CH0-)/2 is the common-mode

input voltage and VOUT is the equivalent input voltage

that the output code translates to, with the ADC transfer

function. In the MCP3918 specification, VCM varies

from -1V to +1V.

4.18

ADC Reset Mode

ADC Reset mode (also called Soft Reset mode) can

only be entered in SPI mode by setting the RESET<0>

bit high in the CONFIG1 register. This mode is defined

as the condition where the converter is active, but its

output is forced to 0.

The registers are not affected in this Reset mode and

retain their state, except for the data registers of the

corresponding channel, which are reset to 0.

The ADC can immediately output meaningful codes

after leaving the Reset mode (and after the sinc filter

settling time). This mode is both entered and exited

through bit settings in CONFIG1 register.

The configuration registers are not modified by the Soft

Reset mode. While in Reset mode, no Data Ready

pulse will be generated by the ADC.

When the ADC exits ADC Reset mode, any phase

delay present before reset was entered will still be

present.

However, when the ADC is in Soft Reset mode, the

input structure is still clocking if MCLK is applied in

order to properly bias the inputs, so that no leakage

current is observed. If MCLK is not applied, large

analog input leakage currents can be observed for

highly negative input voltages (typically below -0.6V

referred to AGND).

PSRR dB



V

OUT

AV

-------------------





log

CMRR dB



V

OUT

V

-----------------





log

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