MCP3918 datasheet(35/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 35

MCP3918

FIGURE 5-4:

Sinc Filter Frequency

Response, OSR = 256, MCLK = 4 MHz,

PRE<1:0> = 00.

FIGURE 5-5:

Sinc Filter Frequency

Response, OSR = 4096 (in pink), OSR = 512 (in

blue), MCLK = 4 MHz, PRE<1:0> = 00.

5.5

ADC Output Coding

The second-order modulator, SINC3+SINC1 filter,

PGA, VREF and the analog input structure all work

together to produce the device transfer function for the

analog-to-digital conversion (see Equation 5-3).

The output data is calculated on 24-bit (23-bit plus sign)

and coded in two's complement format, MSB first. The

output format can then be modified by the

WIDTH_DATA<1:0> settings in the STATUSCOM

(see Section 9.5 “STATUSCOM Register - Status

and Communication Register”

for more information).

case

positive

saturation

(CH0+ – CH0-

>VREF/1.5), the output code is locked to 7FFFFF for

24-bit

mode.

case

negative

saturation

(CH0+ - CH0- < -VREF/1.5), the output code is locked

to 800000 for 24-bit mode.

Equation 5-3 is only true for DC inputs. For AC inputs,

this transfer function needs to be multiplied by the

transfer function of the SINC3+SINC1 filter (see

Equations 5-1 and 5-3).

EQUATION 5-3:

For data formats other than the default 24-bit format,

Equation 5-3 should be multiplied by a scaling factor,

depending on the data format used (defined by

WIDTH_DATA<1:0>). The data format and the

associated scaling factors are given in Figure 5-6.

TABLE 5-4:

OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME

OSR<2:0>

OSR3

OSR1

Total OSR

Resolution in Bits

(No Missing Code)

Settling Time

-3 dB Bandwidth

000

96/DMCLK

0.26*DRCLK

001

192/DMCLK

0.26*DRCLK

010

128

384/DMCLK

0.26*DRCLK

011

256

768/DMCLK

0.26*DRCLK

100

512

1536/DMCLK

0.26*DRCLK

101

512

1024

2048/DMCLK

0.37*DRCLK

110

512

2048

3072/DMCLK

0.42*DRCLK

111

512

4096

5120/DMCLK

0.43*DRCLK

-80

-60

-40

-20

-120

-100

100

1000

10000

100000

Input Frequency (Hz)

-100

-80

-60

-40

-20

-160

-140

-120

100

10000

1000000

Input Frequency (Hz)

For 24-bit Mode, WIDTH_DATA<1:0> = 01 (Default)

DATA_CH0

–

REF+

RE F-

–

-------------------------------------





8388 608





1.5



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