MCP3918 datasheet(41/88 Pages) MICROCHIP

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DS20005287A-page 41

MCP3918

5.12

Digital System Offset and Gain

Errors

The MCP3918 incorporates two sets of additional

registers to perform system digital offset and gain error

calibration, which will modify the output result of the

channel, if calibration is enabled. The gain and offset

calibrations can be enabled or disabled through two

configuration bits (EN_OFFCAL and EN_GAINCAL).

When both calibrations are enabled, the output of the

ADC is modified per Equation 5-8. These calibrations

are not effective in 2-Wire interface mode.

EQUATION 5-8:

DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS

CALCULATIONS

5.12.1

DIGITAL OFFSET ERROR

CALIBRATION

The OFFCAL_CH0 register is 23-bit plus sign two’s

complement registers, whose LSB value is the same as

the Channel ADC Data. This register is then added bit

by bit to the ADC output codes, if the EN_OFFCAL bit

is enabled. Enabling the EN_OFFCAL bit does not

create a pipeline delay; the offset addition is

instantaneous. For low OSR values, only the significant

digits are added to the output (up to the resolution of

the ADC; for example, at OSR = 32, only the first 17

bits are added).

The offset is not added when the corresponding

channel is in Reset or Shutdown mode. The

corresponding input voltage offset value added by each

LSB in these 24-bit registers is:

EQUATION 5-9:

This register is a “Don't Care” if EN_OFFCAL = 0

(offset calibration disabled), but its value is not cleared

by the EN_OFFCAL bit.

5.12.2

DIGITAL GAIN ERROR

CALIBRATION

This register is a signed 24-bit MSB – first register

coded with a range of -1x to +(1 - 2-23)x (from

0x800000 to 0x7FFFFF). The gain calibration adds 1x

to this register and multiplies it to the output code of the

channel bit by bit, after offset calibration. Thus, the gain

calibration ranges from 0x to 1.9999999x (from

0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23

increment in the multiplier.

Enabling EN_GAINCAL creates a pipeline delay of

24 DMCLK periods on all channels. All Data Ready

pulses are delayed by 24 DMCLK periods, starting

from data ready pulse following the command enabling

EN_GAINCAL bit. The gain calibration is effective on

the next data ready pulse following the command

enabling EN_GAINCAL bit.

The digital gain calibration does not function when the

corresponding channel is in Reset or Shutdown mode.

The gain multiplier value for an LSB in this 24-bit

EQUATION 5-10:

This register is a “Don't Care” if EN_GAINCAL = 0

(offset calibration disabled), but its value is not cleared

by the EN_GAINCAL bit.

The output data is kept to either 7FFF or 8000 (16-bit

mode) or 7FFFFF or 800000 (24-bit mode) if the output

results are out of bounds after all calibrations are

performed.

DATA_CH0 post

cal

–



DATA_CH0 pre

cal

–

 OFFCAL_CH0



GAINCAL_CH0





OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608)

GAIN (1LSB) = 1/8388608

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