MCP3918 datasheet(58/88 Pages) MICROCHIP

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MCP3918

DS20005287A-page 58

 2014 Microchip Technology Inc.

7.4

Watchdog Timer Reset, Resetting

the Part when in 2-Wire Mode

When the part has entered 2-Wire mode, the Hard

Reset mode functionality is not available because the

RESET pin becomes the logic input for OSR0. If the

user wants to execute a full reset of the part without

doing a POR, the 2-Wire mode incorporates an internal

watchdog timer that automatically performs a full reset

of the part, provided that the timer has elapsed.

The watchdog timer starts synchronously with each

rising edge of SCK/MCLK. If the SCK logic high state is

maintained for a time that is larger than tWATCH, the

watchdog timer circuit forces the full reset of the chip,

which then returns to its default configuration with the

ADC being reset. If the SCK logic high state is

maintained for a time shorter than tWATCH and then

SCK/MCLK toggles to logic low, the internal timer is

cleared, waiting for another rising edge to restart.

The watchdog timer functionality induces a restriction

in the usable range of frequencies on SCK/MCLK. In

order to avoid intermittent resets in all cases, the

minimum SCK/MCLK frequency in 2-Wire Interface

mode is equal to the inverse of the minimum tWATCH

time (1/(2 x 3.6 µs) = 138.9 kHz, if the duty cycle of the

SCK/MCLK is 50%).

The watchdog timer starts only on the rising edge of

SCK/MCLK, not on the falling edge. Maintaining

SCK/MCLK at a logic low state for large periods of time

does not create any watchdog timer resets. A

Watchdog Timer Reset is created only when the

SCK/MCLK state is maintained logic high during a long

enough period of time.

This watchdog timer period permits exiting the 2-Wire

interface, if desired, by toggling the OSC2/MODE pin to

logic low before creating the Watchdog Timer Reset

and maintaining it logic low until the reset occurs.

MCP3918 Datenblatt(PDF) 58 Page - Microchip Technology