MCP3918 datasheet(39/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 39

MCP3918

5.8

Hard Reset Effect on Delta-Sigma

Modulator/Sinc Filter

In SPI mode, when the RESET pin is logic low, the ADC

will be in Reset and the output code is 0x0000h. The

RESET pin performs a hard reset (DC biases are still

on, part is ready to convert) and clears all charges

contained

the

delta-sigma

modulator.

The

comparator’s output is ‘0011’ for the ADC.

The sinc filter is reset, as well as its double output

buffers. This pin is independent of the serial interface.

It brings all the registers to the default state. When

RESET is logic low, any write with the SPI interface will

be disabled and will have no effect. All output pins

(SDO, DR) are high-impedance.

If MCLK is applied, the input structure is enabled and is

properly biasing the substrate of the input transistors.

In this case, the leakage current on the analog inputs is

low if the analog input voltages are kept between -1V

and +1V.

If MCLK is not applied when in Reset mode, the

leakage can be high if the analog inputs are

below -0.6V, as referred to AGND.

5.9

Phase Delay Block

The MCP3918 incorporates a phase delay generator

which ensures the ADC (CH0) converts the inputs after

a fixed delay, as determined by the PHASE register

setting.

The PHASE register contains a 12-bit bank that

represents group delay of the ADC channel (in addition

to the settling time of the sinc filter) expressed in

DMCLK periods with an offset of OSR/2 periods. It is

coded with a 11-bit plus sign, MSB-first two's

complement code. This code indicates how many

DMCLK periods are induced as a delay (see

Equation 5-5).

EQUATION 5-5:

The timing resolution of the phase delay is 1/DMCLK or

1 µs in the default configuration with MCLK = 4 MHz.

Given the definition of DMCLK, the phase delay is

affected by a change in the prescaler settings

(PRE<1:0>) and the MCLK frequency. The Data Ready

signal is affected by the phase delay settings.

5.9.1

PHASE DELAY LIMITS

The limits of the phase delays are determined by the

OSR settings: the phase delays can only go from 0 to

+(OSR-1) DMCLK periods when taking the last reset as

a reference (same definition as MCP391X but not

showing an odd channel reference here since there is

only one channel).

If larger delays are needed, they can be implemented

externally to the chip with an MCU. A FIFO in the MCU

can save incoming data from the ADC channel for a

number N of DRCLK clocks. In this case, DRCLK

would represent the coarse timing resolution, and

DMCLK the fine timing resolution. The total delay will

then be equal to:

EQUATION 5-6:

The Phase delay register can be programmed once

with the OSR = 4096 setting, and will automatically

adjust the OSR afterwards, without the need to change

the value of the PHASE register.

• OSR = 4096: The delay can go from 0 to +4095.

PHASE<11> is the sign bit. Phase<10> is the

MSB and PHASE<0> the LSB.

• OSR = 2048: The delay can go from 0 to +2047.

PHASE<10> is the sign bit. Phase<9> is the MSB

and PHASE<0> the LSB.

• OSR = 1024: The delay can go from 0 to +1023.

PHASE<9> is the sign bit. Phase<8> is the MSB

and PHASE<0> the LSB.

• OSR = 512: The delay can go from 0 to +511

PHASE<8> is the sign bit. Phase<7> is the MSB

and PHASE<0> the LSB.

• OSR = 256: The delay can go from 0 to +255.

PHASE<7> is the sign bit. Phase<6> is the MSB

and PHASE<0> the LSB.

• OSR = 128: The delay can go from 0 to +127.

PHASE<6> is the sign bit. Phase<5> is the MSB

and PHASE<0> the LSB.

• OSR = 64: The delay can go from 0 to +63.

PHASE<5> is the sign bit. Phase<4> is the MSB

and PHASE<0> the LSB.

• OSR = 32: The delay can go from 0 to +31.

PHASE<4> is the sign bit. Phase<3> is the MSB

and PHASE<0> the LSB.

Total Delay

PHASE<11:0> Decimal Code

OSR

-----------

DMCLK

--------------------------------------------------------------------------------------------

Note:

Rewriting the PHASE register with the

same value automatically resets and

restarts the ADC.

Total Delay = N/DRCLK + OSR/2/DMCLK

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