MCP3918 datasheet(31/88 Pages) MICROCHIP

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DS20005287A-page 31

MCP3918

5.0

DEVICE OVERVIEW

5.1

Analog Inputs (CH0+/-)

The MCP3918 analog inputs can be connected directly

to current and voltage transducers (such as shunts,

current transformers or Rogowski coils). Each input pin

is protected by specialized ESD structures that allow

bipolar ±2V continuous voltage, with respect to AGND,

to be present at their inputs without the risk of perma-

nent damage.

The ADC has fully differential voltage inputs for better

noise performance. The absolute voltage at each pin

relative to AGND should be maintained in the ±1V range

during operation in order to ensure the specified ADC

accuracy. The common mode signals should be

adapted to respect both the previous conditions and

the differential input voltage range. For best

performance, the common mode signals should be

maintained to AGND.

5.2

Programmable Gain Amplifiers

(PGA)

The Programmable Gain Amplifier (PGA) resides at the

front-end of the delta-sigma ADC. It has two functions:

translate the common-mode voltage of the input from

AGND to an internal level between AGND and AVDD, and

amplify the input differential signal. The translation of

the common-mode voltage does not change the

differential signal, but recenters the common mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the delta-sigma

modulator must not be exceeded. The PGA of the ADC

is controlled by the PGA_CH0<2:0> bits in the GAIN

PGA.

5.3

Delta-Sigma Modulator

5.3.1

ARCHITECTURE

The ADC includes a proprietary second-order

modulator with a multi-bit 5-level DAC architecture (see

Figure 5-1). The quantizer is a Flash ADC composed of

four comparators with equally spaced thresholds and a

thermometer output coding. The proprietary five-level

architecture ensures minimum quantization noise at

the outputs of the modulators without disturbing

linearity or inducing additional distortion. The sampling

frequency

DMCLK

(typically

1 MHz

with

MCLK = 4 MHz) so the modulators are refreshed at a

DMCLK rate.

Figure 5-1 represents a simplified block diagram of the

delta-sigma ADC present on MCP3918.

FIGURE 5-1:

Simplified Delta-Sigma ADC

Block Diagram.

Note:

If the analog inputs are held to a potential

of -0.6 to -1V for extended periods of time,

MCLK must be present inside the device

in order to avoid large leakage currents at

the analog inputs. This is true even during

Hard Reset mode or during the Soft Reset

of the ADC. However, during the

Shutdown mode of the ADC or during the

POR state, the clock is not distributed

inside the circuit. During these states, it is

recommended to keep the analog input

voltages above -0.6V referred to AGND in

order to avoid high analog inputs leakage

currents.

TABLE 5-1:

PGA CONFIGURATION

SETTING

Gain

PGA_CH0<2:0>

Gain

(V/V)

Gain

(dB)

VIN Range (V)

±0.6

±0.3

412

±0.15

818

±0.075

±0.0375

±0.01875

Note:

The two undefined settings are G = 1. This

table is defined with VREF =1.2V.

Second-

Order

Integrator

Loop

Filter

Quantizer

DAC

Differential

Voltage Input

Output

Bit Stream

5-level

Flash ADC

MCP3918 Delta-Sigma Modulator

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