MCP3918 datasheet(49/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 49

MCP3918

6.5.2

CONTINUOUS WRITE

The STATUSCOM register contains the write loop

settings for the internal register address pointer

(WRITE). For the Continuous Write modes, the

address selection can take the two following values:

SDO is always in a high-impedance state during a

continuous write

communication. Writing

to a

non-writable address (such as addresses 0x00 to 0x07

or any of the unused register’s addresses) has no

effect and does not increment the address pointer. In

this case, the user needs to stop the communication

and restart a communication with a Control byte

pointing to a writable address (0x08 to 0x1F).

6.6

Situations that Reset and Restart

Active ADC

Immediately after the following actions, the active ADC

(the ones not in Soft Reset or Shutdown modes) is

reset and automatically restarted in order to provide

proper operation:

Change in PHASE register

Overwrite of the same PHASE register value

Change in the OSR<2:0> settings

Change in the PRE<1:0> settings

Change in the CLKEXT setting

Change in the VREFEXT setting

After these temporary resets, the ADC goes back to

normal operation, with no need for an additional

command. Each ADC data output register is cleared

during this process. The PHASE register can be used

to serially soft reset the ADC, without using the RESET

bit in the CONFIG1 register, if the same value is written

in the PHASE register.

6.7

Data Ready Pin (DR)

To communicate when channel data is ready for

transmission, the Data Ready signal is available on the

Data Ready (DR) pin at the end of a conversion. The

DR pin outputs an active-low pulse with a pulse width

equal to half a DMCLK clock period. After a Data Ready

pulse falling edge has occurred, the ADC output data is

updated within the tDODR timing and can then be read

through SPI communication.

The first Data Ready pulse after a Hard or a Soft Reset

is located after the settling time of the sinc filter (see

Table 5-4) plus the phase delay of the corresponding

channel (see Section 5.11 “Crystal Oscillator”).

Each subsequent pulse is then periodic, and the period

is equal to a DRCLK clock period (see Equation 4-3

and Figure 1-3). The Data Ready pulse is always

synchronous with the internal DRCLK clock.

The DR pin can be used as an interrupt pin when

connected to an MCU or DSP, which will synchronize

the readings of the ADC data outputs. When not

active-low, this pin can be either in high-impedance

(when DR_HIZ = 0) or in a defined logic high state

(when DR_HIZ = 1). This is controlled through the

STATUSCOM register. This allows multiple devices to

share the same DR pin (with a pull-up resistor

connected between DR and DVDD). If only the

MCP3918 device is connected on the interrupt bus, the

DR pin does not require a pull-up resistor, and

therefore it is recommended to use the DR_HIZ = 1

configuration for such applications.

The CS pin has no effect over the DR pin, which means

that, even if the CS pin is logic high, the Data Ready

pulses coming from the active ADC channels will still

be provided; the DR pin behavior is independent from

the SPI interface. While the RESET pin is logic low, the

DR pin is not active. The DR pin is latched in the logic

low state when the interrupt flag on the CRCREG is

present to signal that the desired register configuration

has been corrupted (see Section 6.11 “Detecting

Configuration Change through CRC-16 Checksum

on Register Map and its Associated Interrupt

Flag”

TABLE 6-2:

ADDRESS SELECTION IN

CONTINUOUS WRITE

WRITE

Continuous Write Communications

Static (No incrementation)

Types (Default)

Note:

When LOCK<7:0> is different from 0xA5,

all the addresses, except for 0x1F,

become non-writable (see Section 6.10

“Locking/Unlocking

Map

Write Access”

)

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