MCP3918 datasheet(67/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 67

MCP3918

9.1

CHANNEL Register –

ADC Channel Data

Output Register

The ADC Channel Data Output register always

contains the most recent A/D conversion data. This

ADC read communication occurs. When a data ready

event occurs during a read communication, the most

current ADC data is also latched to avoid data

corruption issues. The three bytes of each channel are

updated synchronously at a DRCLK rate. They can be

accessed separately, if needed, but are refreshed

synchronously.

Name

Bits

Address

Cof.

CHANNEL0

0x00

CHANNEL REGISTER

R-0

DATA_CH0

<23> (MSB)

DATA_CH0

<22>

DATA_CH0

<21>

DATA_CH0

<20>

DATA_CH0

<19>

DATA_CH0

<18>

DATA_CH0

<17>

DATA_CH0

<16>

bit 23

bit 16

R-0

DATA_CH0

<15>

DATA_CH0

<14>

DATA_CH0

<13>

DATA_CH0

<12>

DATA_CH0

<11>

DATA_CH0

<10>

DATA_CH0

<9>

DATA_CH0

<8>

bit 15

bit 8

R-0

DATA_CH0

<7>

DATA_CH0

<6>

DATA_CH0

<5>

DATA_CH0

<4>

DATA_CH0

<3>

DATA_CH0

<2>

DATA_CH0

<1>

DATA_CH0

<0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-0

DATA_CH0:

Output code from ADC. This data is post-calibration if the EN_OFFCAL or EN_GAINCAL

bits are enabled. This data can be formatted in 16-/24-/32-bit modes, depending on the WIDTH_-

DATA<1:0> settings. (See Section 5.5 “ADC Output Coding”.)

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