MCP3918 datasheet(19/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 19

MCP3918

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

3.1

Master Reset/OSR0 Logic Input

(RESET/OSR0)

In SPI mode, this pin is active low and places the entire

chip in a Reset state when active.

When RESET is logic low, all registers are reset to their

default value, no communication can take place, and

no clock is distributed inside the part, except in the

input structure if MCLK is applied (if MCLK is idle, then

no clock is distributed). This state is equivalent to a

Power-On Reset (POR) state.

Since the default state of the ADC is on, the analog

power consumption when RESET is logic low is

equivalent to when RESET is logic high. Only the digital

power consumption is largely reduced because this

current consumption is essentially dynamic and is

reduced drastically when there is no clock running.

If MCLK is applied when RESET is logic low, all the

analog biases are enabled during a reset, so that the

part is fully operational just after a RESET rising edge.

If MCLK is not applied, there is a time after a hard reset

when the conversion may not accurately correspond to

the start-up of the input structure.

This input is Schmitt-triggered.

In 2-Wire Interface mode, this is the OSR0 logic select

pin (see Section 7.0 “2-Wire Serial Interface

Description”

for the logic input table for OSR0 and

OSR1). The pin state is latched when the MODE

changes to 2-Wire Interface mode, and is relatched at

each watchdog timer reset.

TABLE 3-1:

SIX-CHANNEL MCP3918 PIN FUNCTION TABLE

MCP3918

SSOP

MCP3918

QFN

Symbol

Function

RESET/OSR0

Master Reset Logic Input Pin or OSR0 Logic Input Pin

219

DVDD

Digital Power Supply Pin

320

AVDD

Analog Power Supply Pin

CH0+

Non-Inverting Analog Input Pin for Channel 0

CH0-

Inverting Analog Input Pin for Channel 0

Not connected

AGND

Analog Ground Pin, Return Path for internal analog circuitry

REFIN+/OUT

Non-Inverting Voltage Reference Input and Internal Reference

Output Pin

REFIN-

Inverting Voltage Reference Input Pin

DGND

Digital Ground Pin, Return Path for internal digital circuitry

Not connected

MDAT0

Modulator Data Output Pin for Channel 0

DR/GAIN1

Data Ready Signal Output Pin or GAIN1 Logic Input Pin

OSC1/CLKI/GAIN0 Oscillator Crystal Connection Pin or External Clock Input Pin or

GAIN0 Logic Input Pin

OSC2/MODE

Oscillator Crystal Connection Input Pin or Serial Interface Mode

Logic Input Pin

CS/BOOST

Serial Interface Chip Select Input Pin or BOOST Logic Input Pin

SCK/MCLK

Serial Interface Clock Pin or Master Clock Input Pin

SDO

Serial Interface Data Input Pin

SDI/OSR1

Serial Interface Data Input Pin or OSR1 Logic Input Pin

—

Exposed Thermal Pad

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