MCP3918 datasheet(37/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005287A-page 37

MCP3918

5.6

Voltage Reference

5.6.1

INTERNAL VOLTAGE REFERENCE

The MCP3918 contains an internal voltage reference

source specially designed to minimize drift over

temperature. In order to enable the internal voltage

reference, the VREFEXT bit in the CONFIG1 register

must be set to ‘0’ (default mode). This internal VREF

supplies reference voltage to all channels. The typical

value of this voltage reference is 1.2V ± 2%. The

internal reference has a very low typical temperature

coefficient of ±7 ppm/°C, allowing the output to have

minimal variation, with respect to temperature, since

they are proportional to (1/VREF).

The noise of the internal voltage reference is low

enough not to significantly degrade the SNR of the

ADC, if compared to a precision external low-noise

voltage reference. The output pin for the internal

voltage reference is REFIN+/OUT.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not necessary for keeping ADC accuracy, but a minimal

0.1 µF ceramic capacitance can be connected to avoid

EMI/EMC susceptibility issues due to the antenna

created by the REFIN+/OUT pin, if left floating.

The bypass capacitors also help in applications where

the voltage reference output is connected to other

circuits. In this case, additional buffering may be

needed, since the output drive capability of this output

is low.

Adding too much capacitance on the REFIN+/OUT pin

may slightly degrade the THD performance of the ADC.

5.6.2

DIFFERENTIAL EXTERNAL

VOLTAGE INPUTS

When the VREFEXT bit is set to ‘1’, the two reference

pins (REFIN+/OUT, REFIN-) become a differential

voltage

reference

input.

The

voltage

the

REFIN+/OUT is noted VREF+, and the voltage at the

REFIN- pin is noted VREF-. The differential voltage

input value is given by Equation 5-4.

EQUATION 5-4:

The specified VREF ranges from 1.1V to 1.3V. The

REFIN- pin voltage (VREF-) should be limited to ±0.1V,

with respect to AGND. Typically, for single-ended

reference applications, the REFIN- pin should be

directly connected to AGND, with its own separate track

to avoid any spike due to switching noise.

5.6.3

TEMPERATURE COMPENSATION

(VREFCAL<7:0>)

The internal voltage reference consists of a proprietary

circuit and algorithm to compensate for first-order and

second-order

temperature

coefficients.

The

compensation

enables

very

low

temperature

coefficients (typically 9 ppm/°C) on the entire range of

temperatures, from - 40°C to +125°C. This temperature

coefficient varies from part to part.

This temperature coefficient can be adjusted on each

part through the VREFCAL<7:0> bits present in the

CONFIG0 register (bits 7 to 0). These register settings

are only for advanced users. The VREFCAL<7:0> bits

should not be modified unless the user wants to

calibrate the temperature coefficient of the whole

system or application. The default value of this register

is set to 0x50. The default value (0x50) was chosen to

optimize the standard deviation of the tempco across

process variation. The value can be slightly improved

to around 7 ppm/°C if the VREFCAL<7:0> bits are

written at 0x42, but this setting degrades the standard

deviation of the VREF tempco.The typical variation of

the temperature coefficient of the internal voltage

reference with respect to the VREFCAL register code

is given by Figure 5-6. Modifying the value stored in the

VREFCAL<7:0> bits may also vary the voltage

reference, in addition to the temperature coefficient.

TABLE 5-8:

OSR = 32 OUTPUT CODE EXAMPLES

ADC Output Code (MSB First)

Hexadecimal

Decimal,

17-bit Resolution

0111

1111

1 0 0 0

0 0 0 0

0x7FFF80

+ 65, 535

0111

1111

0 0 0 0

0x7FFF00

+ 65, 534

0000

0 0 0 0

0x000000

1111

1 0 0 0

0 0 0 0

0xFFFF80

-1

1000

0000

1 0 0 0

0 0 0 0

0x800080

- 65,535

1000

0000

0 0 0 0

0x800000

- 65, 536

VREF =VREF+– VREF-

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