MCP3918 datasheet(50/88 Pages) MICROCHIP

50 / 88 page

MCP3918

DS20005287A-page 50

 2014 Microchip Technology Inc.

6.8

ADC Channel Latching and

Synchronization

The ADC data output register (address 0x00) has a

double buffer output structure. The two sets of latches

in series are triggered by the data ready signal and an

internal signal indicating the beginning of a read

communication sequence (read start).

The first set of latches holds the ADC channel data

output register when the data is ready. This behavior is

synchronous with the MCLK clock.

The second set of latches ensures that, when reading

starts on an ADC output, the corresponding data is

latched, so that no data corruption can occur within a

read. This behavior is synchronous with the SCK clock.

If an ADC read has started, in order to read the

following ADC output, the current reading needs to be

fully completed (all bits must be read on the SDO pin

from the ADC output data registers).

Since the double output buffer structure is triggered

with two events that depend on two asynchronous

clocks (data ready pulse with MCLK and read start with

SCK), it is recommended to implement one of the three

following methods on the MCU or the processor, in

order to synchronize the reading of the channels:

Use the DR pin pulses as an interrupt

: once a

falling edge occurs on the DR pin, the data is

available for reading on the ADC output

registers after the tDODR timing. If this timing is

not respected, data corruption can occur.

Use a timer clocked with MCLK as a

synchronization event:

since the data ready

pulse is synchronous with MCLK, the user can

calculate the position of the data ready pulse

depending on the PHASE, the OSR<2:0> and

the PRE<1:0> settings. Again, the tDODR timing

needs to be added to this calculation, to avoid

data corruption.

Poll the DRSTATUS bit in the STATUSCOM

this method consists of continuously

reading the STATUSCOM register and waiting

for the DRSTATUS bit to be equal to '0'. When

this event happens, the user can start a new

communication to read the desired ADC data. In

this case, no additional timing is required.

The first method is the preferred one, as it can be used

without adding additional MCU code space, but

requires connecting the DR pin to an I/O pin of the

MCU. The two last methods require more MCU code

space and execution time, but they allow synchronizing

the reading of the channels without connecting the DR

pin, which saves one I/O pin on the MCU.

6.9

Securing Read Communications

through CRC-16 Checksum

Since power/energy metering systems can generate or

receive large EMI/EMC interferences and large

transient spikes, it is helpful to secure SPI

communications as much as possible to maintain data

integrity and desired configurations during the lifetime

of the application.

The communication data on the SDO pin can be

secured through the insertion of a Cyclic Redundancy

Check (CRC) checksum at the end of each continuous

reading sequence. The CRC checksum on the

communications can be enabled or disabled through

the EN_CRCCOM bit in the STATUSCOM register. The

CRC message ensures the integrity of the read

sequence bits transmitted on the SDO pin, and the

CRC checksum is inserted in between each read

sequence (see Figure 6-10).

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