MCP3918 datasheet(56/88 Pages) MICROCHIP

56 / 88 page

MCP3918

DS20005287A-page 56

 2014 Microchip Technology Inc.

7.2

2-Wire Mode Configuration

Settings

When the user wants to exclusively use the 2-Wire

Interface mode in digitally isolated applications, the

OSC2 pin should always be in a logic high state,

starting from the power-up of the part. Otherwise, the

user can change the interface mode by toggling the

OSC2/MODE pin within a POR, a Hard Reset or a

Watchdog Timer Reset; the MODE is latched when

exiting one of these three types of reset. When the part

has entered 2-Wire mode, the entire part configuration

keeps its default settings (see Section 9.0 “MCP3918

Internal Registers”

for the default settings of all

internal registers), except for the configuration of the

Gain in Channel 0, the OSR and the BOOST settings.

2-Wire

mode,

the

input

pins

OSR0/OSR1/BOOST/GAIN0/GAIN1 are latched on

the OSC2/MODE rising edge and should typically be

directly connected to DVDD or DGND, depending on the

desired configuration. These pins define the only

configurable settings in 2-Wire mode. If more settings

are required by the application, it is recommended to

use the SPI mode. The following tables describe the

configuration options for these five pins.

7.2.1

OSR1/OSR0

OSR

Setting

Logic

Pins.

These

inputs

are

Schmitt-triggered.

7.2.2

BOOST

Current Boost Setting Logic Pin. This input is

Schmitt-triggered.

7.2.3

GAIN1/GAIN0

PGA Gain Setting Logic Pins. These inputs are

Schmitt-triggered.

7.3

2-Wire Communication Protocol

In 2-Wire mode, the SCK/MCLK pin needs to be

clocked continuously at all times for proper operation.

Any change in the clock frequency will lead to

degraded THD/SFDR specifications. The part obeys

the same timing specifications in both SPI and 2-Wire

Interface mode for SCK/SDO pins. The MCLK

maximum input frequency is 10 MHz in 2-Wire mode,

since the converter still respects Table 5-2 for

maximum AMCLK frequency (provided the part has

entered 2-Wire mode at power-up). Since the MCLK is

divided internally, the part accepts a wide range of duty

cycles for the SCK input, provided the serial interface

timings are respected.

In 2-Wire Interface mode, communication uses framed

data sets on the SDO to output data at a fixed data rate,

synchronously with SCK, and using only one output

pin. The frame is different depending on the device and

the oversampling ratio (OSR) selected. When in

OSR = 64 mode, the MCP3918 frame contains the

sync bytes (16-bit), one channel of 16-bit ADC data and

a 16-bit CRC. For OSR = 128 and higher, each frame

is a group of 7 bytes (56 bits), clocked by the serial

clock SCK. Each frame is composed of a sync word (2

bytes), 24-bit data output word (3 bytes) and CRC. The

sync word comes first, followed by Channel 0 ADC

output (DATA_CH0<23:0>) and 16-bit CRC. See

Figures 7-1 and 7-2.

As a verification feature, the sync word contains all

settings coming from the five logic input pins available

(OSR0/1, GAIN0/1, BOOST), in order to provide the

user with the information about this configuration. It

also provides information about the count of the frame

through bits CNT0/1, which is useful when the SDO is

multiplexed at the output of the digital isolators (see

next paragraph). The sync word also contains an

additional sync byte (fixed at 0xA5 value) for additional

security in synchronization and communication.

TABLE 7-1:

OSR SETTINGS

OSR1

OSR0

OSR

128

256

512

TABLE 7-2:

CURRENT BOOST SETTINGS

BOOST PIN

BOOST

0.5x

TABLE 7-3:

CHANNEL 0 GAIN SETTINGS

GAIN1

GAIN0

CH0 PGA GAIN

MCP3918 Datenblatt(PDF) 56 Page - Microchip Technology

MCP3918 Datenblatt(HTML) 56 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datenblatt Download

Link URL