MCP3918 datasheet(52/88 Pages) MICROCHIP

52 / 88 page

MCP3918

DS20005287A-page 52

 2014 Microchip Technology Inc.

6.10

Locking/Unlocking Register Map

Write Access

The MCP3918 digital interface includes an advanced

security feature that allows locking or unlocking the

miscommunications that can corrupt the desired

configuration of the device, especially an SPI read

becoming an SPI write because of the noisy

environment.

The last register address of the register map

(0x1F: LOCK/CRC) contains the LOCK<7:0> bits. If

these bits are equal to the password value (which is

equal to the default value of 0xA5), the register map

write access is not locked. Any write can take place and

communications are not protected.

When the LOCK<7:0> bits are different from 0xA5, the

and therefore the full device configuration are

write-protected. Any write to an address other than

0x1F will yield no result. All the register addresses,

except for 0x1F, become read-only. In this case, if the

user wants to change the configuration, the

LOCK<7:0> bits have to be reprogrammed back to

0xA5 before sending the desired write command.

The LOCK<7:0> bits are located in the last register, so

that the user can program the whole register map,

starting from 0x09 to 0x1E within one continuous write

sequence, and then lock the configuration at the end of

the sequence with writing all zeros, for example in the

0x1F address.

6.11

Detecting Configuration Change

through CRC-16 Checksum on

Interrupt Flag

In order to prevent internal corruption of the register

and to provide additional security on the register map

configuration, the MCP3918 device includes an

automatic and continuous CRC checksum calculation

on the full register map configuration bits. This

calculation is not the same as the communication CRC

checksum described in Section 6.9 “Securing Read

Communications through CRC-16 Checksum”

This calculation takes the full register map as the CRC

message

and

outputs

checksum

the

CRCREG<15:0> bits located in the LOCK/CRC

Since this feature is intended to protect the

configuration of the device, this calculation is run

continuously only when the register map is locked

(LOCK<7:0> different from 0xA5, see Section 6.10

“Locking/Unlocking Register Map Write Access”

If the register map is unlocked, the CRCREG<15:0>

bits are cleared and no CRC is calculated.

The calculation is fully completed in ten DMCLK

periods and refreshed every ten DMCLK periods

continuously. The CRCREG<15:0> bits are reset when

a POR or a hard reset occurs. All the bits contained in

the defined registers from addresses 0x09 to 0x1F are

processed by the CRC engine to give the

CRCREG<15:0>. The DRSTATUS bit is set to '1'

(default) and the CRCREG<15:0> bits are set to '0'

(default) for this calculation engine, as they could vary

during the calculation.

An interrupt flag can be enabled through the EN_INT

bit in the STATUSCOM register and provided on the DR

pin when the configuration has changed without a write

command being processed. This interrupt is a logic low

state. This interrupt is cleared when the register map is

unlocked (since CRC calculation is not processed

anymore).

At power-up, the interrupt is not present and the

writing its configuration, the user needs to lock the

bits) to be able to use the interrupt flag. The

CRCREG<15:0> bits will be calculated for the first time

in 10 DMCLK periods. This first value will then be the

reference checksum value and will be latched

internally, until a hard reset, a POR or an unlocking of

the register map happens. The CRCREG<15:0> will

then be calculated continuously and checked against

the reference checksum. If the CRCREG<15:0> is

different from the reference, the interrupt sends a flag

by setting the DR pin to a logic low state until it is

cleared.

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