RZSLASHT1 datasheet(102/139 Pages) RENESAS

102 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 102 of 139

Jun. 30, 2025

RZ/T1 Group

2. Electrical Characteristics

2.4.5.8

SCIFA Timing

Note 1. tSEcyc: SERICLK cycle

Note 2. When the SEMR.ABCS0 bit = 1 and the SEMR.BGDM bit = 1

Table 2.26

SCIFA Timing

Output load conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF

Item

Symbol min*1

max*1

Unit*1

Test

Conditions

SCIFA

Input clock cycle

Asynchronous

tScyc

4―

tSEcyc

Figure 2.50

Clock

synchronous

―

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rising time

tSCKr

―5

Input clock falling time

tSCKf

―5

Output clock cycle

Asynchronous*2

tScyc

8―

tSEcyc

Clock

synchronous

4―

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rising time

tSCKr

―9

Output clock falling time

tSCKf

―9

Transmit data delay time

Internal clock

tTXD

-10

Figure 2.51

External clock

3 × tSEcyc

4 × tSEcyc + 20

Receive data setup time

Internal clock

tRXS

3 × tSEcyc + 20

―

External clock

tSEcyc + 10

―

Receive data hold time

Internal clock

tRXH

-3 × tSEcyc

―ns

External clock

2 × tSEcyc + 10

―

Figure 2.50

SCK Clock Input Timing

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 0 to 4)

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