RZSLASHT1 datasheet(104/139 Pages) RENESAS

104 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 104 of 139

Jun. 30, 2025

RZ/T1 Group

2. Electrical Characteristics

2.4.5.9

RSPIa Timing

Note 1. tSEcyc: SERICLK cycle

Note 2. N = SPCKD set value + 1 (1 to 8)

Note 3. N = SSLND set value + 1 (1 to 8)

Note 4. The data output delay time may become longer than half a cycle of the RSPCK clock depending on the bit rate setting. Be sure

to satisfy the conditions required for the electrical characteristics of the master device.

Table 2.27

RSPIa Timing

Output load conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF

Item

Symbol*1

Min*1

Max*1

Unit*1

Test

Conditions

RSPIa

RSPCK clock cycle

Master

tSPcyc

4096

tSEcyc

Figure 2.52

Slave*4

4096

RSPCK clock high

level pulse width

Master

tSPCKWH

(tSPcyc – tSPCKR

– tSPCKF) / 2 – 3

―ns

Slave

0.4

―

tSPcyc

RSPCK clock low

level pulse width

Master

tSPCKWL

(tSPcyc – tSPCKR

– tSPCKF) / 2 – 3

―ns

Slave

0.4

―

tSPcyc

RSPCK clock rising/

falling time

Output

tSPCKr,

tSPCKf

―9

Input

―

Data input setup time

Master

tSU

―

Figure 2.53 to

Figure 2.56

Slave

8 – tSEcyc

―

Data input hold time

Master

tSEcyc

―ns

Slave

8 + 2 × tSEcyc

―

SSL setup time

Master

tLEAD

N × tSpcyc – 3*2

N × tSpcyc + 3*2

Slave

―

tSEcyc

SSL hold time

Master

tLAG

N × tSpcyc – 3*3

N × tSpcyc + 3*3

Slave

―

tSEcyc

Data output delay

time

Master

tOD

―6

Slave

―

3 × tSEcyc + 20

Data output hold time

Master

tOH

0―

Slave

―

Continuous

transmission delay

Master

tTD

tSPcyc + 2 × tSEcyc

8 × tSPcyc

+ 2 × tSEcyc

Slave

4 × tSEcyc

―

MOSI, MISO rising/

falling time

Output

tDr, tDf

―9

Input

―

SSL rising/falling time

Output

tSSLr, tSSLf ―9

Input

―

Slave access time

tSA

―4

tSEcyc

Figure 2.55 to

Figure 2.56

Slave output release time

tREL

―3

tSEcyc

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