RZSLASHT1 datasheet(114/139 Pages) RENESAS

114 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 114 of 139

Jun. 30, 2025

RZ/T1 Group

2. Electrical Characteristics

2.4.5.12

Serial Sound Interface Timing

Table 2.30

Serial Sound Interface Timing

Output load conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF

Item

Symbol

Min.

Max.

Unit

Test Conditions

SSI

AUDIO_CLK input frequency

tAUDIO

150

MHz

Output clock cycle

150

64000

Figure 2.65

Input clock cycle

150

64000

Clock high level

tHC

―

Clock low level

tLC

―

Clock rising time

tRC

―25

Data delay time

tDTR

-5

Figure 2.66,

Figure 2.67

Setup time

tSR

―

Hold time

tHTR

―

WS change edge SSITXD0 output delay

TDTRW

―

Figure 2.68

Figure 2.65

Clock Input/Output Timing

Figure 2.66

Transmit/Receive Timing (SSISCK0 Rising Synchronous)

SSISCK0

tHC

tLC

tRC

tI, tO

tSR

tHTR

tDTR

SSISCK0

(input or output)

SSIWS0, SSIRXD0

(input)

SSIWS0, SSITXD0

(output)

RZ/T1 Datenblatt(PDF) 114 Page - Renesas Technology Corp

RZ/T1 Datenblatt(HTML) 114 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL