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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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RZ/T1 Datenblatt(PDF) 112 Page - Renesas Technology Corp |
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RZ/T1 Datenblatt(HTML) 112 Page - Renesas Technology Corp |
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112 / 139 page  R01DS0228EJ0200 Rev.2.00 Page 112 of 139 Jun. 30, 2025 RZ/T1 Group 2. Electrical Characteristics 2.4.5.11 RIICa Timing Note 1. tIICcyc: RIIC internal reference clock (IICɸ) cycle Note 2. The value out of parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 00b while the digital filter is enabled by setting ICFER.NFE = 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by setting ICFER.NFE = 1. Note 3. Cb is the total capacitance of the bus lines. Note 4. The minimum values are not specified for tsr and tsf in Fast-mode. Table 2.29 RIICa Timing Output load conditions: VOL2 = 0.4 V, IOL2 = 3 mA Item symbol min*2 max*2 Unit*1 Test Conditions RIICa (Standard- mode) SCL input cycle time tSCL 6(12) × tIICcyc + 1300 ― ns Figure 2.64 SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 ― ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 ― ns SCL, SDA input rising time tsr ―1000 ns SCL, SDA input falling time tsf ―300 ns SCL, SDA input spike pulse removal time tSP 01(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 ― ns Start condition input hold time tSTAH tIICcyc + 300 ― ns Restart condition input setup time tSTAS 1000 ― ns Stop condition input setup time tSTOS 1000 ― ns Data input setup time tSDAS tIICcyc + 50 ― ns Data input hold time tSDAH 0― ns SCL, SDA capacitive load Cb ―400 pF RIICa (Fast-mode) SCL input cycle time tSCL 6(12) × tIICcyc + 600 ― ns SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 ― ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 ― ns SCL, SDA input rising time tsr ―*4 300 ns SCL, SDA input falling time tsf ―*4 300 ns SCL, SDA input spike pulse removal time tSP 01(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 ― ns Start condition input hold time tSTAH tIICcyc + 300 ― ns Restart condition input setup time tSTAS 300 ― ns Stop condition input setup time tSTOS 300 ― ns Data input setup time tSDAS tIICcyc + 50 ― ns Data input hold time tSDAH 0― ns SCL, SDA capacitive load*3 Cb ―400 pF |
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