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RZ/T1 Datenblatt(PDF) 122 Page - Renesas Technology Corp |
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RZ/T1 Datenblatt(HTML) 122 Page - Renesas Technology Corp |
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122 / 139 page ![]() R01DS0228EJ0200 Rev.2.00 Page 122 of 139 Jun. 30, 2025 RZ/T1 Group 2. Electrical Characteristics 2.4.5.16 Delta-Sigma Interface Timing Note: tDCcyc: One cycle time of the ∆Σ interface clock (DSCLK0, DSCLK1) Table 2.34 ∆Σ Interface Timing Conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF Item Symbol min max Unit Test Conditions DSMIF Clock cycle Master tDScyc 11 tDCcyc Figure 2.79 Slave 66.67 200 ns Clock high level Master tDSCKWH 16 ― ns Slave 26.67 ― ns Clock low level Master tDSCKWL 16 ― ns Slave 26.67 ― ns Setup time Master tSU 15 ― ns Figure 2.80, Figure 2.81 Slave 10 ― ns Hold time Master tH 0― ns Slave 10 ― ns Figure 2.79 Clock Input/Output Timing Figure 2.80 Reception Timing (MCLKn Rising Synchronous) MCLKn tDSCKWH tDSCKWL tDScyc tSU tH MCLKn (input or output) MDATn (input) |
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