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RZ/T1 Datenblatt(PDF) 127 Page - Renesas Technology Corp |
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RZ/T1 Datenblatt(HTML) 127 Page - Renesas Technology Corp |
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127 / 139 page ![]() R01DS0228EJ0200 Rev.2.00 Page 127 of 139 Jun. 30, 2025 RZ/T1 Group 2. Electrical Characteristics Note: The above specified values apply when there is no access to the external bus during A/D conversion. If access proceeds during A/D conversion, values may not fall within the above ranges. Note 1. The conversion time is the total of the sampling time and the comparison time (tSPLSH + tCONV in Figure 43.31 and Figure 43.32 in section 43, 12-Bit A/D Converter (S12ADCa), in the RZ/T1 Group User’s Manual: Hardware). The number of sampling states is indicated for each item in Test Conditions. Note 2. The value in parentheses indicates the sampling time. Note: The above specified values apply when there is no access to the external bus during A/D conversion. If access proceeds during A/D conversion, values may not fall within the above ranges. Note 1. The conversion time is the total of the sampling time and the comparison time (tSPLSH + tCONV in Figure 43.31 and Figure 43.32 in section 43, 12-Bit A/D Converter (S12ADCa), in the RZ/T1 Group User’s Manual: Hardware). The number of sampling states is indicated for each item in Test Conditions. Note 2. The value in parentheses indicates the sampling time. Table 2.38 12-Bit A/D (Unit 1) Conversion Characteristics Item min typ max Unit Test Conditions Resolution 8 ― 12 Bit Conversion time*1 (Operation at PCLKF = 60 MHz) Permissible signal source impedance Max. = 1.0 kΩ 0.883 (0.667)*2 ― ― μs Sampling in 40 states Analog input capacitance ― ― 30 pF Offset error ― ― ±6.0 LSB Full-scale error ― ― ±6.0 LSB Quantization error ― ±0.5 ― LSB Absolute accuracy ― ― ±6.0 LSB DNL differential nonlinearity error ― ― ±3.0 LSB INL integral nonlinearity error ― ― ±4.0 LSB |
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